| Message ID | 20220318144534.17996-19-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver nodes for MT8192 SoC | expand |
Hi Allen, please see my comment below. On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote: > Add display nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ > 1 file changed, 111 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index a77d405dd508..59183fb6c80b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1205,6 +1205,13 @@ > #clock-cells = <1>; > }; > > + mutex: mutex@14001000 { > + compatible = "mediatek,mt8192-disp-mutex"; > + reg = <0 0x14001000 0 0x1000>; > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > + }; > + > smi_common: smi@14002000 { > compatible = "mediatek,mt8192-smi-common"; > reg = <0 0x14002000 0 0x1000>; > @@ -1236,6 +1243,110 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > }; > > + ovl0: ovl@14005000 { > + compatible = "mediatek,mt8192-disp-ovl"; > + reg = <0 0x14005000 0 0x1000>; > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + }; > + > + ovl_2l0: ovl@14006000 { > + compatible = "mediatek,mt8192-disp-ovl-2l"; > + reg = <0 0x14006000 0 0x1000>; > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > + }; > + > + rdma0: rdma@14007000 { > + compatible = "mediatek,mt8192-disp-rdma"; > + reg = <0 0x14007000 0 0x1000>; > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > + mediatek,larb = <&larb0>; > + mediatek,rdma-fifo-size = <5120>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + }; > + > + color0: color@14009000 { > + compatible = "mediatek,mt8192-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; > + > + ccorr0: ccorr@1400a000 { > + compatible = "mediatek,mt8192-disp-ccorr"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@1400b000 { > + compatible = "mediatek,mt8192-disp-aal", > + "mediatek,mt8193-disp-aal"; Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-aal", otherwise the drm driver doesn't even probe. Typos happen, just please make sure you're testing before sending to the list so these kind of issues can be caught earlier. Thanks, Nícolas > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + };
On Mon, 2022-03-21 at 19:26 -0400, Nícolas F. R. A. Prado wrote: > Hi Allen, > > please see my comment below. > > On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote: > > Add display nodes for mt8192 SoC. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 > > +++++++++++++++++++++++ > > 1 file changed, 111 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index a77d405dd508..59183fb6c80b 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -1205,6 +1205,13 @@ > > #clock-cells = <1>; > > }; > > > > + mutex: mutex@14001000 { > > + compatible = "mediatek,mt8192-disp-mutex"; > > + reg = <0 0x14001000 0 0x1000>; > > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > > + }; > > + > > smi_common: smi@14002000 { > > compatible = "mediatek,mt8192-smi-common"; > > reg = <0 0x14002000 0 0x1000>; > > @@ -1236,6 +1243,110 @@ > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > }; > > > > + ovl0: ovl@14005000 { > > + compatible = "mediatek,mt8192-disp-ovl"; > > + reg = <0 0x14005000 0 0x1000>; > > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + }; > > + > > + ovl_2l0: ovl@14006000 { > > + compatible = "mediatek,mt8192-disp-ovl-2l"; > > + reg = <0 0x14006000 0 0x1000>; > > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > > + <&iommu0 > > M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > > + }; > > + > > + rdma0: rdma@14007000 { > > + compatible = "mediatek,mt8192-disp-rdma"; > > + reg = <0 0x14007000 0 0x1000>; > > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > > + mediatek,larb = <&larb0>; > > + mediatek,rdma-fifo-size = <5120>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + }; > > + > > + color0: color@14009000 { > > + compatible = "mediatek,mt8192-disp-color", > > + "mediatek,mt8173-disp-color"; > > + reg = <0 0x14009000 0 0x1000>; > > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > > + }; > > + > > + ccorr0: ccorr@1400a000 { > > + compatible = "mediatek,mt8192-disp-ccorr"; > > + reg = <0 0x1400a000 0 0x1000>; > > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > > + }; > > + > > + aal0: aal@1400b000 { > > + compatible = "mediatek,mt8192-disp-aal", > > + "mediatek,mt8193-disp-aal"; > > Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp- > aal", otherwise > the drm driver doesn't even probe. Typos happen, just please make > sure you're > testing before sending to the list so these kind of issues can be > caught > earlier. > > Thanks, > Nícolas > Hi Nícolas, Thanks for your kindly reminder. There are two compatibles in drivers/gpu/drm/mediatek/mtk_disp_aal.c (mediatek,mt8173-disp-aal adn mediatek,mt8183-disp-aal) In 8192, We should use mediatek,mt8183-disp-aal because of design. Do I need to add some information for this in mediatek,disp.txt? Best regards, Allen > > + reg = <0 0x1400b000 0 0x1000>; > > + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > > + };
On Tue, Mar 22, 2022 at 02:15:28PM +0800, allen-kh.cheng wrote: > On Mon, 2022-03-21 at 19:26 -0400, Nícolas F. R. A. Prado wrote: > > On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote: > > > + aal0: aal@1400b000 { > > > + compatible = "mediatek,mt8192-disp-aal", > > > + "mediatek,mt8193-disp-aal"; > > > > Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp- > > aal", otherwise > > the drm driver doesn't even probe. Typos happen, just please make > > sure you're > > testing before sending to the list so these kind of issues can be > > caught > > earlier. > > > > Thanks, > > Nícolas > > > Hi Nícolas, > > Thanks for your kindly reminder. > > There are two compatibles in drivers/gpu/drm/mediatek/mtk_disp_aal.c > (mediatek,mt8173-disp-aal adn mediatek,mt8183-disp-aal) > > In 8192, We should use mediatek,mt8183-disp-aal because of design. If that's the case, then the mediatek,aal.yaml binding should be fixed. As it currently is, the mt8173 compatible is expected as a fallback for mt8192. [1] > > Do I need to add some information for this in mediatek,disp.txt? Note that the mediatek,disp.txt binding was split into several yaml bindings. The binding for this node is now mediatek,aal.yaml and can be seen in Chun-Kuang Hu's tree [1]. Thanks, Nícolas [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml?h=mediatek-drm-next
On 18/03/2022 15:45, Allen-KH Cheng wrote: > Add display nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ > 1 file changed, 111 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index a77d405dd508..59183fb6c80b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1205,6 +1205,13 @@ > #clock-cells = <1>; > }; > > + mutex: mutex@14001000 { > + compatible = "mediatek,mt8192-disp-mutex"; > + reg = <0 0x14001000 0 0x1000>; > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; We are missing power-domains property. > + }; > + > smi_common: smi@14002000 { > compatible = "mediatek,mt8192-smi-common"; > reg = <0 0x14002000 0 0x1000>; > @@ -1236,6 +1243,110 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > }; > > + ovl0: ovl@14005000 { > + compatible = "mediatek,mt8192-disp-ovl"; > + reg = <0 0x14005000 0 0x1000>; > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + }; > + > + ovl_2l0: ovl@14006000 { > + compatible = "mediatek,mt8192-disp-ovl-2l"; > + reg = <0 0x14006000 0 0x1000>; > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; olv and ovl-2l binding mention that the node should be a sibling of mmsys, but this does not hold anymore, correct? Chun-Kuang can you help to fix the binding description? > + }; > + > + rdma0: rdma@14007000 { > + compatible = "mediatek,mt8192-disp-rdma"; > + reg = <0 0x14007000 0 0x1000>; > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > + mediatek,larb = <&larb0>; > + mediatek,rdma-fifo-size = <5120>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; Same here, bindings says it should be a sibling of mmsys. Apart from that the maximal rdma-fifo-size isn't specified for all SoCs including mt1892. > + }; > + > + color0: color@14009000 { > + compatible = "mediatek,mt8192-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; Same here, binding description needs fixed, please check for other bindings as well. The node here looks good. > + > + ccorr0: ccorr@1400a000 { > + compatible = "mediatek,mt8192-disp-ccorr"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@1400b000 { > + compatible = "mediatek,mt8192-disp-aal", > + "mediatek,mt8193-disp-aal"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + }; > + > + gamma0: gamma@1400c000 { > + compatible = "mediatek,mt8192-disp-gamma", > + "mediatek,mt8183-disp-gamma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + }; > + > + postmask0: postmask@1400d000 { > + compatible = "mediatek,mt8192-disp-postmask"; > + reg = <0 0x1400d000 0 0x1000>; > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; > + iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; No iommus mentioned in binding description. Regards, Matthias > + }; > + > + dither0: dither@1400e000 { > + compatible = "mediatek,mt8192-disp-dither", > + "mediatek,mt8183-disp-dither"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + }; > + > + ovl_2l2: ovl@14014000 { > + compatible = "mediatek,mt8192-disp-ovl-2l"; > + reg = <0 0x14014000 0 0x1000>; > + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; > + }; > + > + rdma4: rdma@14015000 { > + compatible = "mediatek,mt8192-disp-rdma"; > + reg = <0 0x14015000 0 0x1000>; > + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA4>; > + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; > + mediatek,rdma-fifo-size = <2048>; > + }; > + > dpi0: dpi@14016000 { > compatible = "mediatek,mt8192-dpi"; > reg = <0 0x14016000 0 0x1000>;
Hi, Allen and Jason: On Fri, 2022-03-25 at 16:47 +0100, Matthias Brugger wrote: > > On 18/03/2022 15:45, Allen-KH Cheng wrote: > > Add display nodes for mt8192 SoC. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 > > +++++++++++++++++++++++ > > 1 file changed, 111 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index a77d405dd508..59183fb6c80b 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -1205,6 +1205,13 @@ > > #clock-cells = <1>; > > }; > > > > + mutex: mutex@14001000 { > > + compatible = "mediatek,mt8192-disp-mutex"; > > + reg = <0 0x14001000 0 0x1000>; > > + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > > We are missing power-domains property. > > > + }; > > + > > smi_common: smi@14002000 { > > compatible = "mediatek,mt8192-smi-common"; > > reg = <0 0x14002000 0 0x1000>; > > @@ -1236,6 +1243,110 @@ > > power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > }; > > > > + ovl0: ovl@14005000 { > > + compatible = "mediatek,mt8192-disp-ovl"; > > + reg = <0 0x14005000 0 0x1000>; > > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + }; > > + > > + ovl_2l0: ovl@14006000 { > > + compatible = "mediatek,mt8192-disp-ovl-2l"; > > + reg = <0 0x14006000 0 0x1000>; > > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > > + <&iommu0 > > M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > > olv and ovl-2l binding mention that the node should be a sibling of > mmsys, but > this does not hold anymore, correct? Chun-Kuang can you help to fix > the binding > description? The sibling problem since the first version binding document. Would you help to fix this problem? But now the binding patch are in chaos, so you may send patch base on mediatek-drm-fixes [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes Regards, CK > > > + }; > > + > > + rdma0: rdma@14007000 { > > + compatible = "mediatek,mt8192-disp-rdma"; > > + reg = <0 0x14007000 0 0x1000>; > > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > > + mediatek,larb = <&larb0>; > > + mediatek,rdma-fifo-size = <5120>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > Same here, bindings says it should be a sibling of mmsys. Apart from > that the > maximal rdma-fifo-size isn't specified for all SoCs including mt1892. > > > + }; > > + > > + color0: color@14009000 { > > + compatible = "mediatek,mt8192-disp-color", > > + "mediatek,mt8173-disp-color"; > > + reg = <0 0x14009000 0 0x1000>; > > + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > > + }; > > Same here, binding description needs fixed, please check for other > bindings as > well. The node here looks good. > > > + > > + ccorr0: ccorr@1400a000 { > > + compatible = "mediatek,mt8192-disp-ccorr"; > > + reg = <0 0x1400a000 0 0x1000>; > > + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > > + }; > > + > > + aal0: aal@1400b000 { > > + compatible = "mediatek,mt8192-disp-aal", > > + "mediatek,mt8193-disp-aal"; > > + reg = <0 0x1400b000 0 0x1000>; > > + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > > + }; > > + > > + gamma0: gamma@1400c000 { > > + compatible = "mediatek,mt8192-disp-gamma", > > + "mediatek,mt8183-disp-gamma"; > > + reg = <0 0x1400c000 0 0x1000>; > > + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > > + }; > > + > > + postmask0: postmask@1400d000 { > > + compatible = "mediatek,mt8192-disp-postmask"; > > + reg = <0 0x1400d000 0 0x1000>; > > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; > > + iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; > > No iommus mentioned in binding description. > > Regards, > Matthias > > > + }; > > + > > + dither0: dither@1400e000 { > > + compatible = "mediatek,mt8192-disp-dither", > > + "mediatek,mt8183-disp-dither"; > > + reg = <0 0x1400e000 0 0x1000>; > > + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > > + }; > > + > > + ovl_2l2: ovl@14014000 { > > + compatible = "mediatek,mt8192-disp-ovl-2l"; > > + reg = <0 0x14014000 0 0x1000>; > > + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; > > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, > > + <&iommu0 > > M4U_PORT_L1_OVL_2L_RDMA2_HDR>; > > + }; > > + > > + rdma4: rdma@14015000 { > > + compatible = "mediatek,mt8192-disp-rdma"; > > + reg = <0 0x14015000 0 0x1000>; > > + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_DISP_RDMA4>; > > + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; > > + mediatek,rdma-fifo-size = <2048>; > > + }; > > + > > dpi0: dpi@14016000 { > > compatible = "mediatek,mt8192-dpi"; > > reg = <0 0x14016000 0 0x1000>; > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!zVqvfzFDPNKR4JTcN1lwwRDeyBfZrFrweEkoyESipag84FOR5IyZTU7FxVTR5w$ >
On 25/03/2022 16:47, Matthias Brugger wrote: > > > On 18/03/2022 15:45, Allen-KH Cheng wrote: >> Add display nodes for mt8192 SoC. >> >> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> >> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ >> 1 file changed, 111 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >> index a77d405dd508..59183fb6c80b 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >> @@ -1205,6 +1205,13 @@ >> #clock-cells = <1>; >> }; >> + mutex: mutex@14001000 { >> + compatible = "mediatek,mt8192-disp-mutex"; >> + reg = <0 0x14001000 0 0x1000>; >> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; >> + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > > We are missing power-domains property. > >> + }; >> + >> smi_common: smi@14002000 { >> compatible = "mediatek,mt8192-smi-common"; >> reg = <0 0x14002000 0 0x1000>; >> @@ -1236,6 +1243,110 @@ >> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> }; >> + ovl0: ovl@14005000 { >> + compatible = "mediatek,mt8192-disp-ovl"; >> + reg = <0 0x14005000 0 0x1000>; >> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; >> + clocks = <&mmsys CLK_MM_DISP_OVL0>; >> + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, >> + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + }; >> + >> + ovl_2l0: ovl@14006000 { >> + compatible = "mediatek,mt8192-disp-ovl-2l"; >> + reg = <0 0x14006000 0 0x1000>; >> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; >> + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, >> + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > > olv and ovl-2l binding mention that the node should be a sibling of mmsys, but > this does not hold anymore, correct? Chun-Kuang can you help to fix the binding > description? > Forget about the sibling problem I mentioned, the problem is my poor English not the binding description. Regards, Matthias >> + }; >> + >> + rdma0: rdma@14007000 { >> + compatible = "mediatek,mt8192-disp-rdma"; >> + reg = <0 0x14007000 0 0x1000>; >> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; >> + clocks = <&mmsys CLK_MM_DISP_RDMA0>; >> + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; >> + mediatek,larb = <&larb0>; >> + mediatek,rdma-fifo-size = <5120>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > > Same here, bindings says it should be a sibling of mmsys. Apart from that the > maximal rdma-fifo-size isn't specified for all SoCs including mt1892. > >> + }; >> + >> + color0: color@14009000 { >> + compatible = "mediatek,mt8192-disp-color", >> + "mediatek,mt8173-disp-color"; >> + reg = <0 0x14009000 0 0x1000>; >> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_COLOR0>; >> + }; > > Same here, binding description needs fixed, please check for other bindings as > well. The node here looks good. > >> + >> + ccorr0: ccorr@1400a000 { >> + compatible = "mediatek,mt8192-disp-ccorr"; >> + reg = <0 0x1400a000 0 0x1000>; >> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_CCORR0>; >> + }; >> + >> + aal0: aal@1400b000 { >> + compatible = "mediatek,mt8192-disp-aal", >> + "mediatek,mt8193-disp-aal"; >> + reg = <0 0x1400b000 0 0x1000>; >> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_AAL0>; >> + }; >> + >> + gamma0: gamma@1400c000 { >> + compatible = "mediatek,mt8192-disp-gamma", >> + "mediatek,mt8183-disp-gamma"; >> + reg = <0 0x1400c000 0 0x1000>; >> + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; >> + }; >> + >> + postmask0: postmask@1400d000 { >> + compatible = "mediatek,mt8192-disp-postmask"; >> + reg = <0 0x1400d000 0 0x1000>; >> + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; >> + iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; > > No iommus mentioned in binding description. > > Regards, > Matthias > >> + }; >> + >> + dither0: dither@1400e000 { >> + compatible = "mediatek,mt8192-disp-dither", >> + "mediatek,mt8183-disp-dither"; >> + reg = <0 0x1400e000 0 0x1000>; >> + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_DITHER0>; >> + }; >> + >> + ovl_2l2: ovl@14014000 { >> + compatible = "mediatek,mt8192-disp-ovl-2l"; >> + reg = <0 0x14014000 0 0x1000>; >> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; >> + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, >> + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; >> + }; >> + >> + rdma4: rdma@14015000 { >> + compatible = "mediatek,mt8192-disp-rdma"; >> + reg = <0 0x14015000 0 0x1000>; >> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; >> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; >> + clocks = <&mmsys CLK_MM_DISP_RDMA4>; >> + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; >> + mediatek,rdma-fifo-size = <2048>; >> + }; >> + >> dpi0: dpi@14016000 { >> compatible = "mediatek,mt8192-dpi"; >> reg = <0 0x14016000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a77d405dd508..59183fb6c80b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1205,6 +1205,13 @@ #clock-cells = <1>; }; + mutex: mutex@14001000 { + compatible = "mediatek,mt8192-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + }; + smi_common: smi@14002000 { compatible = "mediatek,mt8192-smi-common"; reg = <0 0x14002000 0 0x1000>; @@ -1236,6 +1243,110 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + ovl0: ovl@14005000 { + compatible = "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + ovl_2l0: ovl@14006000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8192-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,larb = <&larb0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + color0: color@14009000 { + compatible = "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@1400a000 { + compatible = "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@1400b000 { + compatible = "mediatek,mt8192-disp-aal", + "mediatek,mt8193-disp-aal"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@1400c000 { + compatible = "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + postmask0: postmask@1400d000 { + compatible = "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; + }; + + dither0: dither@1400e000 { + compatible = "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + }; + + ovl_2l2: ovl@14014000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + }; + + rdma4: rdma@14015000 { + compatible = "mediatek,mt8192-disp-rdma"; + reg = <0 0x14015000 0 0x1000>; + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA4>; + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size = <2048>; + }; + dpi0: dpi@14016000 { compatible = "mediatek,mt8192-dpi"; reg = <0 0x14016000 0 0x1000>;