From patchwork Fri Apr 22 06:01:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12822810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BFD7C433EF for ; Fri, 22 Apr 2022 06:12:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=26bEamF7Bp/TyS67J/QxCToMZda+Yt8LFfm2X0bcEjE=; b=jV46U/X57eT78t vry2MxqVgyS+C/UEik4GGvd5mbx8+rmRJnHykw6E0QASrA4xSNHpX1Psldj+XlsVHTwNYXSw3H5ed pndrtN5I18dYi3Gt0opxHTYZD+gXjmfiOjWkMSH3TCXr9Z9iI8BoxGVwkjy8tAvnZs0k6Wrev07WS K/itjHQZ0hncmrwNjpdvSgGm13B5whi85QyqWg02CZJu5x6YJ2uCswX8X/KoNLoQx/fJUaNaKPALU hDl9SKRKkfs9pVJiJZ/VuU6PyeuW5WFX7xT60Jv8HxGrONX9rlyLBC6NhJIhrUAswT3phWfJMP2hz ePqqxd7Mu35JaME0vpEQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhmWk-00GQ7k-9i; Fri, 22 Apr 2022 06:12:22 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhmTn-00GOr5-NK; Fri, 22 Apr 2022 06:09:21 +0000 X-UUID: c5f354cb198240e49cf888ad45d5fa6b-20220421 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:b62f8129-96d9-4052-bd54-7648e40955c8, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9, CLOUDID:ec7093f0-da02-41b4-b6df-58f4ccd36682, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: c5f354cb198240e49cf888ad45d5fa6b-20220421 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 536072681; Thu, 21 Apr 2022 23:09:11 -0700 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 23:02:07 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Apr 2022 14:02:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Apr 2022 14:02:00 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit Date: Fri, 22 Apr 2022 14:01:49 +0800 Message-ID: <20220422060152.13534-15-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220422060152.13534-1-rex-bc.chen@mediatek.com> References: <20220422060152.13534-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220421_230919_813187_4A45D01C X-CRM114-Status: UNSURE ( 8.50 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org To support reset of infra_ao, add the bit definition for thermal/SVS. Signed-off-by: Rex-BC Chen --- include/dt-bindings/reset/mt8195-resets.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index a26bccc8b957..2479680616fb 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -26,4 +26,11 @@ #define MT8195_TOPRGU_SW_RST_NUM 16 +/* INFRA RST0 */ +#define MT8195_INFRA_RST0_THERMAL_AP_RST 0 +/* INFRA RST3 */ +#define MT8195_INFRA_RST3_PTP_RST 5 +/* INFRA RST4 */ +#define MT8195_INFRA_RST4_THERMAL_MCU_RST 10 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */