| Message ID | 20220426164547.434324-1-fparent@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] arm64: dts: mt8183: add dpi node to mt8183 | expand |
On Tue, 2022-04-26 at 18:45 +0200, Fabien Parent wrote: > From: Pi-Hsun Shih <pihsun@chromium.org> > > Add dpi node to mt8183. > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > v2: no changes > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 4b08691ed39e..49e662e34b36 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -1507,6 +1507,17 @@ dsi0: dsi@14014000 { > phy-names = "dphy"; > }; > > + dpi0: dpi@14015000 { > + compatible = "mediatek,mt8183-dpi"; > + reg = <0 0x14015000 0 0x1000>; > + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&spm > MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DPI_IF>, > + <&mmsys CLK_MM_DPI_MM>, > + <&apmixedsys CLK_APMIXED_TVDPLL>; > + clock-names = "pixel", "engine", "pll"; > + }; > + > mutex: mutex@14016000 { > compatible = "mediatek,mt8183-disp-mutex"; > reg = <0 0x14016000 0 0x1000>; Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Regards, Macpaul Lin
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4b08691ed39e..49e662e34b36 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1507,6 +1507,17 @@ dsi0: dsi@14014000 { phy-names = "dphy"; }; + dpi0: dpi@14015000 { + compatible = "mediatek,mt8183-dpi"; + reg = <0 0x14015000 0 0x1000>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DPI_IF>, + <&mmsys CLK_MM_DPI_MM>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + }; + mutex: mutex@14016000 { compatible = "mediatek,mt8183-disp-mutex"; reg = <0 0x14016000 0 0x1000>;