| Message ID | 20220429143411.7640-3-yf.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek TTBR up to 35bit support | expand |
Hi YF, Thanks very much for this patch. Nearly all the lastest SoC like mt8192/mt8195 support this. On Fri, 2022-04-29 at 22:34 +0800, yf.wang@mediatek.com wrote: > From: Yunfei Wang <yf.wang@mediatek.com> > > Add the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT support, so that > level 2 page table can allocate in normal memory. Could you help comment more detailedly here and in the title?, this patch just allows the level 2 pgtable PA up to 35bits, not only in ZONE_DMA32(GFP_DMA32). > > Signed-off-by: Ning Li <ning.li@mediatek.com> > Signed-off-by: Yunfei Wang <yf.wang@mediatek.com> > Cc: <stable@vger.kernel.org> # 5.10.* If you add this for stable, Which commit do you need for "Fixes:" tag? It looks you add a new feature, rather than fixing a bug of the current kernel. I didn't get a issue report for this. If this is a bug, we need more information like under which condition/SoC the error will occur. The code is ok for me. Thanks. > --- > drivers/iommu/mtk_iommu.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 6fd75a60abd6..27481f562df7 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -118,6 +118,7 @@ > #define WR_THROT_EN BIT(6) > #define HAS_LEGACY_IVRP_PADDR BIT(7) > #define IOVA_34_EN BIT(8) > +#define PGTABLE_L2_PA_35_EN BIT(9) > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) > @@ -401,6 +402,9 @@ static int mtk_iommu_domain_finalise(struct > mtk_iommu_domain *dom, > .iommu_dev = data->dev, > }; > > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_L2_PA_35_EN)) > + dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; > + > if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) > dom->cfg.oas = data->enable_4GB ? 33 : 32; > else > @@ -1038,7 +1042,8 @@ static const struct mtk_iommu_plat_data > mt2712_data = { > > static const struct mtk_iommu_plat_data mt6779_data = { > .m4u_plat = M4U_MT6779, > - .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, > + .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN | > + PGTABLE_L2_PA_35_EN, > .inv_sel_reg = REG_MMU_INV_SEL_GEN2, > .iova_region = single_domain, > .iova_region_nr = ARRAY_SIZE(single_domain),
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 6fd75a60abd6..27481f562df7 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -118,6 +118,7 @@ #define WR_THROT_EN BIT(6) #define HAS_LEGACY_IVRP_PADDR BIT(7) #define IOVA_34_EN BIT(8) +#define PGTABLE_L2_PA_35_EN BIT(9) #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ ((((pdata)->flags) & (_x)) == (_x)) @@ -401,6 +402,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, .iommu_dev = data->dev, }; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_L2_PA_35_EN)) + dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) dom->cfg.oas = data->enable_4GB ? 33 : 32; else @@ -1038,7 +1042,8 @@ static const struct mtk_iommu_plat_data mt2712_data = { static const struct mtk_iommu_plat_data mt6779_data = { .m4u_plat = M4U_MT6779, - .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, + .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN | + PGTABLE_L2_PA_35_EN, .inv_sel_reg = REG_MMU_INV_SEL_GEN2, .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain),