| Message ID | 20220503093856.22250-17-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Cleanup MediaTek clk reset drivers and support MT8192/MT8195 | expand |
On 03/05/2022 11:38, Rex-BC Chen wrote: > We will use mediatek clock reset as infracfg_ao reset instead of > ti-syscon. To support this, remove property of ti reset and add > property of #reset-cells for mediatek clock reset. > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> My understanding is that using the old DTS with a newer kernel wouldn't introduce a regression, correct? Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------ > 1 file changed, 1 insertion(+), 12 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index b57e620c2c72..8e5ac11b19f1 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -10,7 +10,6 @@ > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/phy/phy.h> > #include <dt-bindings/pinctrl/mt8195-pinfunc.h> > -#include <dt-bindings/reset/ti-syscon.h> > > / { > compatible = "mediatek,mt8195"; > @@ -295,17 +294,7 @@ > compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; > reg = <0 0x10001000 0 0x1000>; > #clock-cells = <1>; > - > - infracfg_rst: reset-controller { > - compatible = "ti,syscon-reset"; > - #reset-cells = <1>; > - ti,reset-bits = < > - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ > - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ > - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ > - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ > - >; > - }; > + #reset-cells = <1>; > }; > > pericfg: syscon@10003000 {
On Wed, 2022-06-22 at 19:08 +0800, Matthias Brugger wrote: > > On 03/05/2022 11:38, Rex-BC Chen wrote: > > We will use mediatek clock reset as infracfg_ao reset instead of > > ti-syscon. To support this, remove property of ti reset and add > > property of #reset-cells for mediatek clock reset. > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > My understanding is that using the old DTS with a newer kernel > wouldn't > introduce a regression, correct? > > Applied, thanks! > Hello Matthias, yes, because there is no user for this infra reset controller in upstream mainline. In addition, could you also help to give us some suggestion for Nancy's series? Thanks for your big support! [1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=651900 BRs, Bo-Chen > > --- > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------ > > 1 file changed, 1 insertion(+), 12 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > index b57e620c2c72..8e5ac11b19f1 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > @@ -10,7 +10,6 @@ > > #include <dt-bindings/interrupt-controller/irq.h> > > #include <dt-bindings/phy/phy.h> > > #include <dt-bindings/pinctrl/mt8195-pinfunc.h> > > -#include <dt-bindings/reset/ti-syscon.h> > > > > / { > > compatible = "mediatek,mt8195"; > > @@ -295,17 +294,7 @@ > > compatible = "mediatek,mt8195-infracfg_ao", > > "syscon", "simple-mfd"; > > reg = <0 0x10001000 0 0x1000>; > > #clock-cells = <1>; > > - > > - infracfg_rst: reset-controller { > > - compatible = "ti,syscon-reset"; > > - #reset-cells = <1>; > > - ti,reset-bits = < > > - 0x140 18 0x144 18 0 0 > > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ > > - 0x120 0 0x124 0 0 0 > > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ > > - 0x730 10 0x734 10 0 0 > > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ > > - 0x150 5 0x154 5 0 0 > > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ > > - >; > > - }; > > + #reset-cells = <1>; > > }; > > > > pericfg: syscon@10003000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index b57e620c2c72..8e5ac11b19f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,7 +10,6 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mt8195-pinfunc.h> -#include <dt-bindings/reset/ti-syscon.h> / { compatible = "mediatek,mt8195"; @@ -295,17 +294,7 @@ compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; - - infracfg_rst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = < - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ - >; - }; + #reset-cells = <1>; }; pericfg: syscon@10003000 {