From patchwork Wed May 4 09:14:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12837515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE999C433F5 for ; Wed, 4 May 2022 09:31:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NaRnlsrxVXmsfuFwyao0Y7ERTwUUDehgAra83IC1Ljo=; b=bcu9DPkWoopnv5 XNG1oteDYqTg3sH9P6dGN5stu50zpPUUx0ID2ztHB1u9ZtWfV5OTTJfKfxdOs+awb7HVIFPUNqWyR +9hgGEtZ3A9Ursl5eEusRsP+3GphMoErGItKn2g+HbpM8A47KYJLB5AYMpEf5ayAXUmCGfWDVKHBW mOdHcaKGMJVkMh2NwDdjXsFtocCdUr2puLqER0X3hxRu1B85tpGQbi79RZD52L97PbYr+152vbyc0 CY4EiJDMu2JIqOPHwGPt+02qw0mwuAuV74ceTdyFPv9azJmM+DLh9x1BmFASc71gAzgPpQz7RRq5I uwALZE4W/KLzAZ6Nl3Zw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmBLm-009shn-F8; Wed, 04 May 2022 09:31:14 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmB8C-009kkj-VK; Wed, 04 May 2022 09:17:14 +0000 X-UUID: 0c514fad0d6941e9a35e2581300fb2b1-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:e930b0f2-c548-4898-8206-787dab5a38ca, OB:0, LO B:0,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:8 X-CID-META: VersionHash:faefae9, CLOUDID:f1a174c7-85ee-4ac1-ac05-bd3f1e72e732, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 0c514fad0d6941e9a35e2581300fb2b1-20220504 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1197990035; Wed, 04 May 2022 02:17:00 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 02:14:49 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 17:14:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 17:14:44 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "Nancy . Lin" , "jason-jh . lin" , Yongqiang Niu , , , , , , , , Subject: [PATCH v20 12/25] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Date: Wed, 4 May 2022 17:14:27 +0800 Message-ID: <20220504091440.2052-13-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504091440.2052-1-nancy.lin@mediatek.com> References: <20220504091440.2052-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_021713_031064_33A4E7D0 X-CRM114-Status: GOOD ( 10.92 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements which include MDP_RDMA0~7, MERGE0~3, and ETHDR. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/soc/mediatek/mtk-mutex.c | 33 ++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 4721f0b74d9b..78197ebf5595 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -110,6 +110,24 @@ #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 #define MT8195_MUTEX_MOD_DISP_PWM0 27 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12 +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18 +#define MT8195_MUTEX_MOD_DISP1_DPI0 25 +#define MT8195_MUTEX_MOD_DISP1_DPI1 26 +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27 + #define MT2712_MUTEX_MOD_DISP_PWM2 10 #define MT2712_MUTEX_MOD_DISP_OVL0 11 #define MT2712_MUTEX_MOD_DISP_OVL1 12 @@ -313,6 +331,21 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0, + [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1, + [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2, + [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3, + [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4, + [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5, + [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6, + [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0, + [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1, + [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2, + [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3, + [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {