[v20,25/25] arm64: dts: mt8195: add display node for vdosys1

Message ID	20220504091440.2052-26-nancy.lin@mediatek.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org> From: Nancy.Lin <nancy.lin@mediatek.com> To: Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Chun-Kuang Hu <chunkuang.hu@kernel.org>, "Philipp Zabel" <p.zabel@pengutronix.de>, <wim@linux-watchdog.org>, "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>, <linux@roeck-us.net> CC: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, "Nathan Chancellor" <nathan@kernel.org>, Nick Desaulniers <ndesaulniers@google.com>, "Nancy . Lin" <nancy.lin@mediatek.com>, "jason-jh . lin" <jason-jh.lin@mediatek.com>, Yongqiang Niu <yongqiang.niu@mediatek.com>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <dri-devel@lists.freedesktop.org>, <llvm@lists.linux.dev>, <singo.chang@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com> Subject: [PATCH v20 25/25] arm64: dts: mt8195: add display node for vdosys1 Date: Wed, 4 May 2022 17:14:40 +0800 Message-ID: <20220504091440.2052-26-nancy.lin@mediatek.com> In-Reply-To: <20220504091440.2052-1-nancy.lin@mediatek.com> References: <20220504091440.2052-1-nancy.lin@mediatek.com> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org> Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
Series	Add MediaTek SoC DRM (vdosys1) support for mt8195 \| expand [v20,00/25] Add MediaTek SoC DRM (vdosys1) support for mt8195 [v20,01/25] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 [v20,02/25] dt-bindings: reset: mt8195: add vdosys1 reset control bit [v20,03/25] dt-bindings: mediatek: add ethdr definition for mt8195 [v20,04/25] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components [v20,05/25] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 [v20,06/25] soc: mediatek: add mtk_mmsys_update_bits API [v20,07/25] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 [v20,08/25] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 [v20,09/25] soc: mediatek: mmsys: add mmsys for support 64 reset bits [v20,10/25] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 [v20,11/25] soc: mediatek: add mtk-mutex component - dp_intf1 [v20,12/25] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 [v20,13/25] drm/mediatek: add display MDP RDMA support for MT8195 [v20,14/25] drm/mediatek: add display merge advance config API for MT8195 [v20,15/25] drm/mediatek: add display merge start/stop API for cmdq support [v20,16/25] drm/mediatek: add display merge mute/unmute support for MT8195 [v20,17/25] drm/mediatek: add display merge async reset control [v20,18/25] drm/mediatek: add ETHDR support for MT8195 [v20,19/25] drm/mediatek: add mediatek-drm plane color encoding info [v20,20/25] drm/mediatek: add ovl_adaptor support for MT8195 [v20,21/25] drm/mediatek: add dma dev get function [v20,22/25] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support [v20,23/25] drm/mediatek: add drm ovl_adaptor sub driver for MT8195 [v20,24/25] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 [v20,25/25] arm64: dts: mt8195: add display node for vdosys1

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index dbca699bba05..808b70525497 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mt8195-pinfunc.h> +#include <dt-bindings/reset/mt8195-resets.h> #include <dt-bindings/reset/ti-syscon.h> / { @@ -22,6 +23,22 @@ aliases { gce0 = &gce0; gce1 = &gce1; + ethdr0 = &ethdr0; + mutex0 = &mutex; + mutex1 = &mutex1; + merge1 = &merge1; + merge2 = &merge2; + merge3 = &merge3; + merge4 = &merge4; + merge5 = &merge5; + vdo1-rdma0 = &vdo1_rdma0; + vdo1-rdma1 = &vdo1_rdma1; + vdo1-rdma2 = &vdo1_rdma2; + vdo1-rdma3 = &vdo1_rdma3; + vdo1-rdma4 = &vdo1_rdma4; + vdo1-rdma5 = &vdo1_rdma5; + vdo1-rdma6 = &vdo1_rdma6; + vdo1-rdma7 = &vdo1_rdma7; }; cpus { @@ -1186,9 +1203,217 @@ }; vdosys1: syscon@1c100000 { - compatible = "mediatek,mt8195-vdosys1", "syscon"; + compatible = "mediatek,mt8195-mmsys", "syscon"; reg = <0 0x1c100000 0 0x1000>; + mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; + + mutex1: mutex0@1c101000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c101000 0 0x1000>; + reg-names = "vdo1_mutex"; + interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; + clock-names = "vdo1_mutex"; + mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; + }; + + vdo1_rdma0: mdp-rdma@1c104000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + vdo1_rdma1: mdp-rdma@1c105000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c105000 0 0x1000>; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; + }; + + vdo1_rdma2: mdp-rdma@1c106000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c106000 0 0x1000>; + interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; + }; + + vdo1_rdma3: mdp-rdma@1c107000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c107000 0 0x1000>; + interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; + }; + + vdo1_rdma4: mdp-rdma@1c108000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c108000 0 0x1000>; + interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; + }; + + vdo1_rdma5: mdp-rdma@1c109000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c109000 0 0x1000>; + interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; + }; + + vdo1_rdma6: mdp-rdma@1c10a000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10a000 0 0x1000>; + interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; + }; + + vdo1_rdma7: mdp-rdma@1c10b000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10b000 0 0x1000>; + interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; + }; + + merge1: vpp-merge@1c10c000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10c000 0 0x1000>; + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; + }; + + merge2: vpp-merge@1c10d000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10d000 0 0x1000>; + interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; + }; + + merge3: vpp-merge@1c10e000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10e000 0 0x1000>; + interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; + }; + + merge4: vpp-merge@1c10f000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10f000 0 0x1000>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; + }; + + merge5: vpp-merge@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + }; + + ethdr0: ethdr@1c114000 { + compatible = "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11c000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", + "ethdr_top"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; + reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", + "gfx_fe1_async", "vdo_be_async"; + }; + }; };

[v20,25/25] arm64: dts: mt8195: add display node for vdosys1

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Patch