From patchwork Thu May 12 14:45:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yf.wang@mediatek.com X-Patchwork-Id: 12847814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 969DDC433EF for ; Thu, 12 May 2022 14:59:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ct6KLQp1kRBx8F9uQUXsE0l7dZaevrViXQRcCG+kshs=; b=M47Z8IrqD0Xclt KJg0T59oshGJDtkDlqH2hwbtZ/LnrUC73nxsbNvUfzUwg1UG5pJMsnoyJMKUfNC5iZa864pxogaVQ iOWts8Rwzw4rdS7p5VQAB75Qq6YwE/9L3cMm8gN3XrGwatoSeT0PSZ0RMlm9j4k1t7vkCCa60nsY8 6uT8B3orEmnc0LcEfc2kEpr55V6jBB/sK2Bg/ISvt2ICoMrU4XHSMSqsxLOV/23YfK/Y4PIvkAt8Q HddNoWgGF++Z3/dkHLjdpWDG9JNKRnf7VN0PEYZu7Z7lBqcGidgp9ArhD36f+5PW/L8zlnFrMX+kV L8uOnpw6Neie+GnhDBLA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1npAHZ-00CXI1-1f; Thu, 12 May 2022 14:59:13 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1npAHW-00CXGw-Q0; Thu, 12 May 2022 14:59:12 +0000 X-UUID: 6c2ec7fdc9c04be9ad7592d7cf082cf5-20220512 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:dc37053d-7418-4ee1-9c4f-c5979d8ef499, OB:0, LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:faefae9, CLOUDID:d2d314a7-eab7-4b74-a74d-5359964535a9, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 6c2ec7fdc9c04be9ad7592d7cf082cf5-20220512 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1620724226; Thu, 12 May 2022 07:59:05 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 May 2022 07:52:54 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 12 May 2022 22:52:52 +0800 Received: from mbjsdccf07.mediatek.inc (10.15.20.246) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 May 2022 22:52:50 +0800 From: To: Yong Wu , Joerg Roedel , "Will Deacon" , Matthias Brugger , "open list:MEDIATEK IOMMU DRIVER" , "moderated list:MEDIATEK IOMMU DRIVER" , "moderated list:ARM/Mediatek SoC support" , "open list" CC: , Libo Kang , Yong Wu , Yunfei Wang , Ning Li Subject: [PATCH v3 2/2] iomm/mediatek: Allow page table PA up to 35bit Date: Thu, 12 May 2022 22:45:56 +0800 Message-ID: <20220512144557.18025-3-yf.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220512144557.18025-1-yf.wang@mediatek.com> References: <20220512144557.18025-1-yf.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220512_075910_874485_A082FB26 X-CRM114-Status: GOOD ( 14.65 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Yunfei Wang Add the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT support, so that allows page table PA up to 35bit, not only in ZONE_DMA32. Signed-off-by: Ning Li Signed-off-by: Yunfei Wang --- drivers/iommu/mtk_iommu.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 6fd75a60abd6..1b9a876ef271 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -33,6 +33,7 @@ #define REG_MMU_PT_BASE_ADDR 0x000 #define MMU_PT_ADDR_MASK GENMASK(31, 7) +#define MMU_PT_ADDR_2_0_MASK GENMASK(2, 0) #define REG_MMU_INVALIDATE 0x020 #define F_ALL_INVLD 0x2 @@ -118,6 +119,7 @@ #define WR_THROT_EN BIT(6) #define HAS_LEGACY_IVRP_PADDR BIT(7) #define IOVA_34_EN BIT(8) +#define PGTABLE_PA_35_EN BIT(9) #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ ((((pdata)->flags) & (_x)) == (_x)) @@ -401,6 +403,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, .iommu_dev = data->dev, }; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) + dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) dom->cfg.oas = data->enable_4GB ? 33 : 32; else @@ -450,6 +455,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, struct mtk_iommu_domain *dom = to_mtk_domain(domain); struct device *m4udev = data->dev; int ret, domid; + u32 regval; domid = mtk_iommu_get_domain_id(dev, data->plat_data); if (domid < 0) @@ -472,8 +478,14 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, return ret; } data->m4u_dom = dom; - writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, - data->base + REG_MMU_PT_BASE_ADDR); + + /* Bits[6:3] are invalid for mediatek platform */ + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) + regval = (dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK) | + (dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_2_0_MASK); + else + regval = dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK; + writel(regval, data->base + REG_MMU_PT_BASE_ADDR); pm_runtime_put(m4udev); } @@ -987,6 +999,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) struct mtk_iommu_suspend_reg *reg = &data->reg; struct mtk_iommu_domain *m4u_dom = data->m4u_dom; void __iomem *base = data->base; + u32 regval; int ret; ret = clk_prepare_enable(data->bclk); @@ -1010,7 +1023,14 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); + + /* Bits[6:3] are invalid for mediatek platform */ + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) + regval = (m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK) | + (m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_2_0_MASK); + else + regval = m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK; + writel(regval, base + REG_MMU_PT_BASE_ADDR); /* * Users may allocate dma buffer before they call pm_runtime_get, @@ -1038,7 +1058,8 @@ static const struct mtk_iommu_plat_data mt2712_data = { static const struct mtk_iommu_plat_data mt6779_data = { .m4u_plat = M4U_MT6779, - .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, + .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN | + PGTABLE_PA_35_EN, .inv_sel_reg = REG_MMU_INV_SEL_GEN2, .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain),