@@ -388,6 +388,10 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
}
}
+ atomic_set(&dev->dec_active_cnt, 0);
+ memset(dev->vdec_racing_info, 0, sizeof(dev->vdec_racing_info));
+ mutex_init(&dev->dec_racing_info_mutex);
+
ret = video_register_device(vfd_dec, VFL_TYPE_VIDEO, -1);
if (ret) {
mtk_v4l2_err("Failed to register video device");
@@ -144,6 +144,34 @@ static void mtk_vcodec_dec_disable_irq(struct mtk_vcodec_dev *vdec_dev, int hw_i
}
}
+static void mtk_vcodec_load_racing_info(struct mtk_vcodec_ctx *ctx)
+{
+ void __iomem *vdec_racing_addr;
+ int j;
+
+ mutex_lock(&ctx->dev->dec_racing_info_mutex);
+ if (atomic_inc_return(&ctx->dev->dec_active_cnt) == 1) {
+ vdec_racing_addr = ctx->dev->reg_base[VDEC_MISC] + 0x100;
+ for (j = 0; j < 132; j++)
+ writel(ctx->dev->vdec_racing_info[j], vdec_racing_addr + j * 4);
+ }
+ mutex_unlock(&ctx->dev->dec_racing_info_mutex);
+}
+
+static void mtk_vcodec_record_racing_info(struct mtk_vcodec_ctx *ctx)
+{
+ void __iomem *vdec_racing_addr;
+ int j;
+
+ mutex_lock(&ctx->dev->dec_racing_info_mutex);
+ if (atomic_dec_and_test(&ctx->dev->dec_active_cnt)) {
+ vdec_racing_addr = ctx->dev->reg_base[VDEC_MISC] + 0x100;
+ for (j = 0; j < 132; j++)
+ ctx->dev->vdec_racing_info[j] = readl(vdec_racing_addr + j * 4);
+ }
+ mutex_unlock(&ctx->dev->dec_racing_info_mutex);
+}
+
static struct mtk_vcodec_pm *mtk_vcodec_dec_get_pm(struct mtk_vcodec_dev *vdec_dev,
int hw_idx)
{
@@ -214,11 +242,17 @@ void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx)
mtk_vcodec_dec_child_dev_on(ctx->dev, hw_idx);
mtk_vcodec_dec_enable_irq(ctx->dev, hw_idx);
+
+ if (IS_VDEC_INNER_RACING(ctx->dev->dec_capability))
+ mtk_vcodec_load_racing_info(ctx);
}
EXPORT_SYMBOL_GPL(mtk_vcodec_dec_enable_hardware);
void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx)
{
+ if (IS_VDEC_INNER_RACING(ctx->dev->dec_capability))
+ mtk_vcodec_record_racing_info(ctx);
+
mtk_vcodec_dec_disable_irq(ctx->dev, hw_idx);
mtk_vcodec_dec_child_dev_off(ctx->dev, hw_idx);
@@ -28,6 +28,7 @@
#define MTK_V4L2_BENCHMARK 0
#define WAIT_INTR_TIMEOUT_MS 1000
#define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >= MTK_VDEC_LAT_SINGLE_CORE)
+#define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_RACING)
/*
* enum mtk_hw_reg_idx - MTK hw register base index
@@ -357,6 +358,7 @@ enum mtk_vdec_format_types {
MTK_VDEC_FORMAT_H264_SLICE = 0x100,
MTK_VDEC_FORMAT_VP8_FRAME = 0x200,
MTK_VDEC_FORMAT_VP9_FRAME = 0x400,
+ MTK_VCODEC_INNER_RACING = 0x20000,
};
/**
@@ -478,6 +480,10 @@ struct mtk_vcodec_enc_pdata {
* @subdev_dev: subdev hardware device
* @subdev_prob_done: check whether all used hw device is prob done
* @subdev_bitmap: used to record hardware is ready or not
+ *
+ * @dec_active_cnt: used to mark whether need to record register value
+ * @vdec_racing_info: record register value
+ * @dec_racing_info_mutex: mutex lock used for inner racing mode
*/
struct mtk_vcodec_dev {
struct v4l2_device v4l2_dev;
@@ -523,6 +529,11 @@ struct mtk_vcodec_dev {
void *subdev_dev[MTK_VDEC_HW_MAX];
int (*subdev_prob_done)(struct mtk_vcodec_dev *vdec_dev);
DECLARE_BITMAP(subdev_bitmap, MTK_VDEC_HW_MAX);
+
+ atomic_t dec_active_cnt;
+ u32 vdec_racing_info[132];
+ /* Protects access to vdec_racing_info data */
+ struct mutex dec_racing_info_mutex;
};
static inline struct mtk_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
@@ -626,6 +626,17 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
goto err_scp_decode;
}
+ share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
+ inst->vsi->wdma_end_addr_offset;
+ share_info->trans_start = inst->ctx->msg_queue.wdma_wptr_addr;
+ share_info->nal_info = inst->vsi->dec.nal_info;
+
+ if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
+ memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params,
+ sizeof(share_info->h264_slice_params));
+ vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf);
+ }
+
/* wait decoder done interrupt */
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0);
@@ -639,18 +650,22 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
inst->vsi->wdma_end_addr_offset;
- share_info->trans_start = inst->ctx->msg_queue.wdma_wptr_addr;
- share_info->nal_info = inst->vsi->dec.nal_info;
vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue, share_info->trans_end);
- memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params,
- sizeof(share_info->h264_slice_params));
- vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf);
+ if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
+ memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params,
+ sizeof(share_info->h264_slice_params));
+ vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf);
+ }
+ mtk_vcodec_debug(inst, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->slice_dec_num,
+ inst->vsi->dec.crc[0], inst->vsi->dec.crc[1], inst->vsi->dec.crc[2]);
inst->slice_dec_num++;
return 0;
err_scp_decode:
+ if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability))
+ vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
err_free_fb_out:
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
mtk_vcodec_err(inst, "slice dec number: %d err: %d", inst->slice_dec_num, err);
In order to reduce decoder latency, enable H264 inner racing mode. Send lat trans buffer information to core when trigger lat to work, need not to wait until lat decode done. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> --- .../mediatek/vcodec/mtk_vcodec_dec_drv.c | 4 +++ .../mediatek/vcodec/mtk_vcodec_dec_pm.c | 34 +++++++++++++++++++ .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 11 ++++++ .../vcodec/vdec/vdec_h264_req_multi_if.c | 25 +++++++++++--- 4 files changed, 69 insertions(+), 5 deletions(-)