diff mbox series

[v7,13/19] dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195

Message ID 20220519125527.18544-14-rex-bc.chen@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Cleanup MediaTek clk reset drivers and support SoCs | expand

Commit Message

Rex-BC Chen (陳柏辰) May 19, 2022, 12:55 p.m. UTC 
To support reset of infra_ao, add the index of infra_ao reset of
thermal/svs/pcei for MT8192 and thermal/svs for MT8195.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++
 include/dt-bindings/reset/mt8195-resets.h | 6 ++++++
 2 files changed, 14 insertions(+)

Comments

Rex-BC Chen (陳柏辰) May 20, 2022, 2:58 a.m. UTC | #1 
On Thu, 2022-05-19 at 20:55 +0800, Rex-BC Chen wrote:
> To support reset of infra_ao, add the index of infra_ao reset of
> thermal/svs/pcei for MT8192 and thermal/svs for MT8195.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++
>  include/dt-bindings/reset/mt8195-resets.h | 6 ++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-
> bindings/reset/mt8192-resets.h
> index 764ca9910fa9..12e2087c90a3 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -7,6 +7,7 @@
>  #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
>  #define _DT_BINDINGS_RESET_CONTROLLER_MT8192
>  
> +/* TOPRGU resets */
>  #define MT8192_TOPRGU_MM_SW_RST					
> 1
>  #define MT8192_TOPRGU_MFG_SW_RST				2
>  #define MT8192_TOPRGU_VENC_SW_RST				3
> @@ -30,4 +31,11 @@
>  /* MMSYS resets */
>  #define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
>  
> +/* INFRA resets */
> +#define MT8192_INFRA_RST0_THERM_CTRL_SWRST		0
> +#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST		1
> +#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST	2
> +#define MT8192_INFRA_RST4_PCIE_TOP_SWRST		3
> +#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST	4
> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-
> bindings/reset/mt8195-resets.h
> index a26bccc8b957..0b1937f14b36 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -7,6 +7,7 @@
>  #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
>  #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
>  
> +/* TOPRGU resets */
>  #define MT8195_TOPRGU_CONN_MCU_SW_RST          0
>  #define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
>  #define MT8195_TOPRGU_APU_SW_RST               2
> @@ -26,4 +27,9 @@
>  
>  #define MT8195_TOPRGU_SW_RST_NUM               16
>  
> +/* INFRA resets */
> +#define MT8195_INFRA_RST0_THERM_CTRL_SWRST     0
> +#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
> +#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
> -- 
> 2.18.0
> 

Hello Stephen,

this patch will have conflict with Matthias's commit branch for
include/dt-bindings/reset/mt8192-resets.h.

It's on linux-next.

I have fix it in this version, but I think there will be a merge
conflict if you pick my series in this run.


https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/include/dt-bindings/reset/mt8192-resets.h?h=next-20220519&id=19c66219e4d5b813ebbd28621cfe9c450659ded7

BRs,
Rex
Chen-Yu Tsai May 20, 2022, 3:10 a.m. UTC | #2 
On Fri, May 20, 2022 at 10:58 AM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
>
> On Thu, 2022-05-19 at 20:55 +0800, Rex-BC Chen wrote:
> > To support reset of infra_ao, add the index of infra_ao reset of
> > thermal/svs/pcei for MT8192 and thermal/svs for MT8195.
> >
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++
> >  include/dt-bindings/reset/mt8195-resets.h | 6 ++++++
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-
> > bindings/reset/mt8192-resets.h
> > index 764ca9910fa9..12e2087c90a3 100644
> > --- a/include/dt-bindings/reset/mt8192-resets.h
> > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > @@ -7,6 +7,7 @@
> >  #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
> >  #define _DT_BINDINGS_RESET_CONTROLLER_MT8192
> >
> > +/* TOPRGU resets */
> >  #define MT8192_TOPRGU_MM_SW_RST
> > 1
> >  #define MT8192_TOPRGU_MFG_SW_RST                             2
> >  #define MT8192_TOPRGU_VENC_SW_RST                            3
> > @@ -30,4 +31,11 @@
> >  /* MMSYS resets */
> >  #define MT8192_MMSYS_SW0_RST_B_DISP_DSI0                     15
> >
> > +/* INFRA resets */
> > +#define MT8192_INFRA_RST0_THERM_CTRL_SWRST           0
> > +#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST            1
> > +#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST       2
> > +#define MT8192_INFRA_RST4_PCIE_TOP_SWRST             3
> > +#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST       4
> > +
> >  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> > diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-
> > bindings/reset/mt8195-resets.h
> > index a26bccc8b957..0b1937f14b36 100644
> > --- a/include/dt-bindings/reset/mt8195-resets.h
> > +++ b/include/dt-bindings/reset/mt8195-resets.h
> > @@ -7,6 +7,7 @@
> >  #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
> >  #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
> >
> > +/* TOPRGU resets */
> >  #define MT8195_TOPRGU_CONN_MCU_SW_RST          0
> >  #define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
> >  #define MT8195_TOPRGU_APU_SW_RST               2
> > @@ -26,4 +27,9 @@
> >
> >  #define MT8195_TOPRGU_SW_RST_NUM               16
> >
> > +/* INFRA resets */
> > +#define MT8195_INFRA_RST0_THERM_CTRL_SWRST     0
> > +#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
> > +#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
> > +
> >  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
> > --
> > 2.18.0
> >
>
> Hello Stephen,
>
> this patch will have conflict with Matthias's commit branch for
> include/dt-bindings/reset/mt8192-resets.h.
>
> It's on linux-next.
>
> I have fix it in this version, but I think there will be a merge
> conflict if you pick my series in this run.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/include/dt-bindings/reset/mt8192-resets.h?h=next-20220519&id=19c66219e4d5b813ebbd28621cfe9c450659ded7

The commit in question is in Matthias's v5.18-next/dts64 branch, which also
has the v5.18-next-dts64 tag. The PR for this tag was already picked up
by the soc maintainers, so I guess we could consider it stable.

Matthias, what do you think? Give an ack for the patch to go through the
clk tree with the tag merged in as dependency? There's a compile time
dependency between this and the next patch so we can't just split them
into different trees.


ChenYu
Rex-BC Chen (陳柏辰) May 23, 2022, 5:14 a.m. UTC | #3 
On Sat, 2022-05-21 at 12:23 +0800, Stephen Boyd wrote:
> Quoting Chen-Yu Tsai (2022-05-19 20:10:35)
> > On Fri, May 20, 2022 at 10:58 AM Rex-BC Chen <
> > rex-bc.chen@mediatek.com> wrote:
> > > 
> > > 
> > > Hello Stephen,
> > > 
> > > this patch will have conflict with Matthias's commit branch for
> > > include/dt-bindings/reset/mt8192-resets.h.
> > > 
> > > It's on linux-next.
> > > 
> > > I have fix it in this version, but I think there will be a merge
> > > conflict if you pick my series in this run.
> > > 
> > > 
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/include/dt-bindings/reset/mt8192-resets.h?h=next-20220519&id=19c66219e4d5b813ebbd28621cfe9c450659ded7__;!!CTRNKA9wMg0ARbw!xFfRxOWRAvhQMzoKxqRu8xFsMZLpVZEoK0WZBKeMOoeRGBjKphSL2tox-8zWlRwytjtEImTo1VB1f38wwj8XSlyKIw$
> > >  
> > 
> > The commit in question is in Matthias's v5.18-next/dts64 branch,
> > which also
> > has the v5.18-next-dts64 tag. The PR for this tag was already
> > picked up
> > by the soc maintainers, so I guess we could consider it stable.
> > 
> > Matthias, what do you think? Give an ack for the patch to go
> > through the
> > clk tree with the tag merged in as dependency? There's a compile
> > time
> > dependency between this and the next patch so we can't just split
> > them
> > into different trees.
> > 
> 
> It's pretty late to land something that has cross tree dependencies
> like
> that so I guess we'll just take up this patch series after the merge
> window closes.

Hello Stephen,

Thanks for your big help!
I will send v8 to modify comments from Nícolas.

BRs,
Rex
diff mbox series

Patch

diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index 764ca9910fa9..12e2087c90a3 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -7,6 +7,7 @@ 
 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192
 
+/* TOPRGU resets */
 #define MT8192_TOPRGU_MM_SW_RST					1
 #define MT8192_TOPRGU_MFG_SW_RST				2
 #define MT8192_TOPRGU_VENC_SW_RST				3
@@ -30,4 +31,11 @@ 
 /* MMSYS resets */
 #define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
 
+/* INFRA resets */
+#define MT8192_INFRA_RST0_THERM_CTRL_SWRST		0
+#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST		1
+#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST	2
+#define MT8192_INFRA_RST4_PCIE_TOP_SWRST		3
+#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST	4
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..0b1937f14b36 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -7,6 +7,7 @@ 
 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
 #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
 
+/* TOPRGU resets */
 #define MT8195_TOPRGU_CONN_MCU_SW_RST          0
 #define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
 #define MT8195_TOPRGU_APU_SW_RST               2
@@ -26,4 +27,9 @@ 
 
 #define MT8195_TOPRGU_SW_RST_NUM               16
 
+/* INFRA resets */
+#define MT8195_INFRA_RST0_THERM_CTRL_SWRST     0
+#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
+#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */