From patchwork Mon May 23 06:00:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12858704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 208C7C433F5 for ; Mon, 23 May 2022 09:44:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LFtPyjk+hhYVqKROf5h8b9bb1JpdvJ8k8UC9N7YgnMo=; b=bSEtL3n0SmacXa q5Ijwa+wvoKnKsDc6qmIXIgmKnzXGJ3u634rAeqe4E34HnhW1NTJ8S/rmFOdSZ20N1CiBu4SU0ulL GcRaVDatwBw+RSRlD34QvQkB1Ji/OEt6qsJGZmq3xAsALbECuJ7oZAmJ8UcqGEjapftG5Uuew/AJ9 4B4jJU46YXvdHF50add6zllG27eski2V5ZTw8A9YE3xaqty+jvAsi8s+JycircZqqFFbkqSiZ8HXZ Y0cMqVHnS+/s02Nr1aaRjn2sh/8Svo8tM3rUUfmRYACirViDSTGgGqk/+joiLMLycxxHmXwjmXrGC vgHCEZ8fEH1RYd9PB8hg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt4c1-002wfr-Fl; Mon, 23 May 2022 09:44:29 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt2oU-002AAA-Q6; Mon, 23 May 2022 07:49:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=HCX2efpq710v8eOBrRT9KB0JLNwSyBN8tLHaE9YHUcU=; b=OUAYHXh7MvYHBQtjgT2yjDi+No T5BftpU9jo1QA26mVFbuusj08PEjNrcoJWsix5VojxuhNdBjfv0rx5yXcb1nbgnr8IQrGNLpPMKtv 6BcNPrQ2ASnO/6tWxMYaXrEiinh/lcBXgwPkzgWo/d/qo/Qdvk/F3IcWUGTNKYLzeRM+N5uFksjnW K3owej6Zsmje+MDTQx0ooWTm1bVWurMihxo1Hf/qgLmGnr/27CitvXa2JnsR+jWsflKVVjTsut+MO pmzT8ppR8jM/Lgro/uuPCk61uJibHuGUuPvQdiLZrSVfsKqA/PP6c/7P8MYCCIF5Y47tuONJTuPM7 rjoIQtFQ==; Received: from mailgw01.mediatek.com ([216.200.240.184]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt1Hq-000szs-3u; Mon, 23 May 2022 06:11:29 +0000 X-UUID: c935a03a98dd448f94198cdf4a6ad9e5-20220522 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:3b415194-56c5-46db-b03d-1df9a0739df4, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:2a19b09, CLOUDID:1aff2ee3-edbf-4bd4-8a34-dfc5f7bb086d, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: c935a03a98dd448f94198cdf4a6ad9e5-20220522 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 900951577; Sun, 22 May 2022 23:10:52 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 22 May 2022 23:01:00 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 23 May 2022 14:00:58 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 23 May 2022 14:00:58 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v8 07/19] clk: mediatek: reset: Support nonsequence base offsets of reset registers Date: Mon, 23 May 2022 14:00:44 +0800 Message-ID: <20220523060056.24396-8-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220523060056.24396-1-rex-bc.chen@mediatek.com> References: <20220523060056.24396-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_071126_823280_364B2F6B X-CRM114-Status: GOOD ( 13.05 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado --- drivers/clk/mediatek/clk-mt2701-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701-g3d.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701.c | 11 +++++++---- drivers/clk/mediatek/clk-mt2712.c | 11 +++++++---- drivers/clk/mediatek/clk-mt7622-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt7622-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt7622.c | 11 +++++++---- drivers/clk/mediatek/clk-mt7629-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt7629-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt8135.c | 11 +++++++---- drivers/clk/mediatek/clk-mt8173.c | 11 +++++++---- drivers/clk/mediatek/clk-mt8183.c | 14 ++++++++++++-- drivers/clk/mediatek/reset.c | 11 ++++++----- drivers/clk/mediatek/reset.h | 6 ++++-- 15 files changed, 85 insertions(+), 43 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 270d15ce58bf..b4e7f38860d0 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -36,10 +36,12 @@ static const struct mtk_gate eth_clks[] = { GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static const struct of_device_id of_match_clk_mt2701_eth[] = { diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 9cfd589939e5..1431fa76a0f8 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -35,10 +35,12 @@ static const struct mtk_gate g3d_clks[] = { GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; +static u16 rst_ofs[] = { 0xc, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0xc, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt2701_g3dsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index a6b812fcc922..60bda56a102c 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -33,10 +33,12 @@ static const struct mtk_gate hif_clks[] = { GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static const struct of_device_id of_match_clk_mt2701_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index f165126232d3..6c7a80fb4349 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -735,18 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = pericfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), }, }; diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index c7a8aafd44cc..fd310c375fdf 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1258,18 +1258,21 @@ static const struct mtk_pll_data plls[] = { 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infra */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* peri */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = pericfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), }, }; diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 40eefed3d12b..90d55f882215 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -65,10 +65,12 @@ static const struct mtk_gate sgmii_clks[] = { "ssusb_cdr_fb", 5), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7622_ethsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index ca29d93ce2d0..489b64725b22 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -76,10 +76,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 115db564a6d4..0cba74d38499 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -610,18 +610,21 @@ static struct mtk_composite peri_muxes[] = { MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), }; +static u16 infrasys_rst_ofs[] = { 0x30, }; +static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = pericfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), }, }; diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index c20c7853500d..11b346c9d916 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -76,10 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = { } }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7629_ethsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 5d7ec861afab..c0583043710f 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -71,10 +71,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index f554574b2567..b68888a034c4 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -514,18 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = { MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = pericfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), } }; diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 1e86210e9c66..b8529ee7199d 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -819,18 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = { GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = pericfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), } }; diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 5708c5d8b300..5bc738f4d0e7 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -20,6 +20,9 @@ /* Infra global controller reset set register */ #define INFRA_RST0_SET_OFFSET 0x120 +#define INFRA_RST1_SET_OFFSET 0x130 +#define INFRA_RST2_SET_OFFSET 0x140 +#define INFRA_RST3_SET_OFFSET 0x150 static DEFINE_SPINLOCK(mt8183_clk_lock); @@ -1153,10 +1156,17 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), }; +static u16 infra_rst_ofs[] = { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, +}; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SET_CLR, - .rst_bank_nr = 4, - .reg_ofs = INFRA_RST0_SET_OFFSET, + .rst_bank_ofs = infra_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), }; static int clk_mt8183_apmixed_probe(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 47bc6b1842fd..11b2f74f121d 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -24,8 +24,8 @@ static int mtk_reset_update(struct reset_controller_dev *rcdev, unsigned int val = deassert ? 0 : ~0; return regmap_update_bits(data->regmap, - data->desc->reg_ofs + ((id / 32) << 2), - BIT(id % 32), val); + data->desc->rst_bank_ofs[id / RST_NR_PER_BANK], + BIT(id % RST_NR_PER_BANK), val); } static int mtk_reset_assert(struct reset_controller_dev *rcdev, @@ -58,8 +58,9 @@ static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev, unsigned int deassert_ofs = deassert ? 0x4 : 0; return regmap_write(data->regmap, - data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs, - BIT(id % 32)); + data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] + + deassert_ofs, + BIT(id % RST_NR_PER_BANK)); } static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, @@ -135,7 +136,7 @@ void mtk_register_reset_controller(struct device_node *np, data->desc = desc; data->regmap = regmap; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = desc->rst_bank_nr * 32; + data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK; data->rcdev.ops = rcops; data->rcdev.of_node = np; diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index b4c2b468da4a..d991510ae2d8 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -9,6 +9,8 @@ #include #include +#define RST_NR_PER_BANK 32 + /** * enum mtk_reset_version - Version of MediaTek clock reset controller. * @MTK_RST_SIMPLE: Use the same registers for bit set and clear. @@ -24,12 +26,12 @@ enum mtk_reset_version { /** * struct mtk_clk_rst_desc - Description of MediaTek clock reset. * @version: Reset version which is defined in enum mtk_reset_version. - * @reg_ofs: Base offset of the reset register. + * @rst_bank_ofs: Pointer to an array containing base offsets of the reset register. * @rst_bank_nr: Quantity of reset bank. */ struct mtk_clk_rst_desc { enum mtk_reset_version version; - u16 reg_ofs; + u16 *rst_bank_ofs; u32 rst_bank_nr; };