| Message ID | 20220609104001.97753-4-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek Helio X10 MT6795 - M4U/IOMMU Support | expand |
On Thu, 2022-06-09 at 12:40 +0200, AngeloGioacchino Del Regno wrote: > Add support for the M4Us found in the MT6795 Helio X10 SoC. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> Retitle to: iommu/mediatek: Xxx, then Reviewed-by: Yong Wu <yong.wu@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 8611cf8e4bd5..beca1c5a6c10 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -160,6 +160,7 @@ > enum mtk_iommu_plat { > M4U_MT2712, > M4U_MT6779, > + M4U_MT6795, > M4U_MT8167, > M4U_MT8173, > M4U_MT8183, > @@ -1424,6 +1425,19 @@ static const struct mtk_iommu_plat_data > mt6779_data = { > .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, > }; > > +static const struct mtk_iommu_plat_data mt6795_data = { > + .m4u_plat = M4U_MT6795, > + .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | > + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | > + TF_PORT_TO_ADDR_MT8173, > + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, > + .banks_num = 1, > + .banks_enable = {true}, > + .iova_region = single_domain, > + .iova_region_nr = ARRAY_SIZE(single_domain), > + .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. > */ > +}; > + > static const struct mtk_iommu_plat_data mt8167_data = { > .m4u_plat = M4U_MT8167, > .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | > MTK_IOMMU_TYPE_MM, > @@ -1536,6 +1550,7 @@ static const struct mtk_iommu_plat_data > mt8195_data_vpp = { > static const struct of_device_id mtk_iommu_of_ids[] = { > { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, > { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, > + { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, > { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, > { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, > { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 8611cf8e4bd5..beca1c5a6c10 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -160,6 +160,7 @@ enum mtk_iommu_plat { M4U_MT2712, M4U_MT6779, + M4U_MT6795, M4U_MT8167, M4U_MT8173, M4U_MT8183, @@ -1424,6 +1425,19 @@ static const struct mtk_iommu_plat_data mt6779_data = { .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, }; +static const struct mtk_iommu_plat_data mt6795_data = { + .m4u_plat = M4U_MT6795, + .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | + TF_PORT_TO_ADDR_MT8173, + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, + .banks_num = 1, + .banks_enable = {true}, + .iova_region = single_domain, + .iova_region_nr = ARRAY_SIZE(single_domain), + .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ +}; + static const struct mtk_iommu_plat_data mt8167_data = { .m4u_plat = M4U_MT8167, .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, @@ -1536,6 +1550,7 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = { static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, + { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
Add support for the M4Us found in the MT6795 Helio X10 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/iommu/mtk_iommu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)