@@ -162,18 +162,6 @@ system_clk: dummy13m {
#clock-cells = <0>;
};
- rtc_clk: dummy32k {
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- #clock-cells = <0>;
- };
-
- uart_clk: dummy26m {
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- #clock-cells = <0>;
- };
-
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
@@ -235,7 +223,7 @@ uart0: serial@11002000 {
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&clk26m>;
status = "disabled";
};
@@ -244,7 +232,7 @@ uart1: serial@11003000 {
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&clk26m>;
status = "disabled";
};
@@ -253,7 +241,7 @@ uart2: serial@11004000 {
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&clk26m>;
status = "disabled";
};
@@ -262,7 +250,7 @@ uart3: serial@11005000 {
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&clk26m>;
status = "disabled";
};
};
Remove the RTC and UART fixed clocks, as these were introduced to temporarily provide a dummy clock to devices: since the two 26M/32K fixed oscillators clocks (which do really exist in the SoC) have been added, there's no reason to keep the aforementioned (and now redundant) dummies in this devicetree. In order to remove the uart dummy clock, it was necessary to also reassign the clock of all UART nodes to clk26m. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-)