diff mbox series

[v2,4/4] arm: dts: mediatek: Set fixed-clock for missing XHCI clocks

Message ID 20220623193702.817996-5-nfraprado@collabora.com (mailing list archive)
State New, archived
Headers show
Series Fixes for dtbs_check warnings on Mediatek XHCI nodes | expand

Commit Message

Nícolas F. R. A. Prado June 23, 2022, 7:37 p.m. UTC 
The XHCI controller hardware always has all clocks wired, however
depending on the SoC, some of them might be fixed (ie not controllable).
These fixed clocks were previously omitted from the devicetree entirely.

In order to better describe the hardware on the devicetree, and to have
a fixed order of clocks for all SoCs, add the missing non-controllable
clocks as phandles to a fixed-clock node.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

---

Changes in v2:
- Added this commit

 arch/arm/boot/dts/mt2701.dtsi | 14 ++++++++++----
 arch/arm/boot/dts/mt7623.dtsi | 14 ++++++++++----
 arch/arm/boot/dts/mt7629.dtsi |  6 ++++--
 3 files changed, 24 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index b8eba3ba153c..1c1b9b5a1d7a 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -611,8 +611,11 @@  usb0: usb@1a1c0000 {
 		reg-names = "mac", "ippc";
 		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
-			 <&topckgen CLK_TOP_ETHIF_SEL>;
-		clock-names = "sys_ck", "ref_ck";
+			 <&topckgen CLK_TOP_ETHIF_SEL>,
+			 <&clk26m>,
+			 <&clk26m>,
+			 <&clk26m>;
+		clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 		status = "disabled";
@@ -651,8 +654,11 @@  usb1: usb@1a240000 {
 		reg-names = "mac", "ippc";
 		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
-			 <&topckgen CLK_TOP_ETHIF_SEL>;
-		clock-names = "sys_ck", "ref_ck";
+			 <&topckgen CLK_TOP_ETHIF_SEL>,
+			 <&clk26m>,
+			 <&clk26m>,
+			 <&clk26m>;
+		clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 		status = "disabled";
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 25d31e40a553..b640e6f4ad2e 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -864,8 +864,11 @@  usb1: usb@1a1c0000 {
 		reg-names = "mac", "ippc";
 		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
-			 <&topckgen CLK_TOP_ETHIF_SEL>;
-		clock-names = "sys_ck", "ref_ck";
+			 <&topckgen CLK_TOP_ETHIF_SEL>,
+			 <&clk26m>,
+			 <&clk26m>,
+			 <&clk26m>;
+		clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 		status = "disabled";
@@ -905,8 +908,11 @@  usb2: usb@1a240000 {
 		reg-names = "mac", "ippc";
 		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
-			 <&topckgen CLK_TOP_ETHIF_SEL>;
-		clock-names = "sys_ck", "ref_ck";
+			 <&topckgen CLK_TOP_ETHIF_SEL>,
+			 <&clk26m>,
+			 <&clk26m>,
+			 <&clk26m>;
+		clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 		status = "disabled";
diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
index 46fc236e1b89..810d1c867b43 100644
--- a/arch/arm/boot/dts/mt7629.dtsi
+++ b/arch/arm/boot/dts/mt7629.dtsi
@@ -315,8 +315,10 @@  ssusb: usb@1a0c0000 {
 			clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 				 <&ssusbsys CLK_SSUSB_REF_EN>,
 				 <&ssusbsys CLK_SSUSB_MCU_EN>,
-				 <&ssusbsys CLK_SSUSB_DMA_EN>;
-			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+				 <&ssusbsys CLK_SSUSB_DMA_EN>,
+				 <&clk20m>;
+			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
+				      "xhci_ck";
 			assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
 					  <&topckgen CLK_TOP_SATA_SEL>,
 					  <&topckgen CLK_TOP_HIF_SEL>;