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Thu, 23 Jun 2022 20:13:29 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 23 Jun 2022 20:09:52 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 24 Jun 2022 11:09:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 24 Jun 2022 11:09:49 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v14 10/15] drm/mediatek: dpi: move the yuv422_en_bit to SoC config Date: Fri, 24 Jun 2022 11:09:41 +0800 Message-ID: <20220624030946.14961-11-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220624030946.14961-1-rex-bc.chen@mediatek.com> References: <20220624030946.14961-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220623_201334_775097_8850D6AA X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Guillaume Ranquet Add flexibility by moving the yuv422 en bit to SoC specific config Signed-off-by: Guillaume Ranquet Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index f168a24f10ce..3a5555a26cd1 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_yc_limit { * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). * @channel_swap_shift: Shift value of channel swap. + * @yuv422_en_bit: Enable bit of yuv422. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -145,6 +146,7 @@ struct mtk_dpi_conf { u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift; + u32 yuv422_en_bit; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -382,7 +384,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); } static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) @@ -846,6 +849,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, }; static const struct mtk_dpi_conf mt2701_conf = { @@ -860,6 +864,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, }; static const struct mtk_dpi_conf mt8183_conf = { @@ -873,6 +878,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, }; static const struct mtk_dpi_conf mt8192_conf = { @@ -886,6 +892,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, }; static int mtk_dpi_probe(struct platform_device *pdev)