From patchwork Mon Aug 15 03:07:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 12943079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01703C00140 for ; Mon, 15 Aug 2022 04:08:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=b3BKeHNHkOmEyqFXi/2yjYXaBJc1kL89uDBD+OeJTSI=; b=gFHZZpM39OgrzNAS52Cotqmv+N qLgoPF/Vr5jMupZyngYtEucPfAVqf3iy8iH6/L+UOwSSHGn4X9V0cXSj1jb/QNOQpIq5AufXEay7x omSY+uJmbm9tZqiAUK/HxSMrnr9Z0zM1c2riD3uxhe0nWiNLiQlfIVqrvHRuGUvFXln4ANRmgEAnJ nS2G7/Aik3OEOfFx35OyXtJ00dX45y8OZ0Np6Rx9oVo0rGNd3TO6LxjMs5Qqu8VH0mpnEAd/8bPUy WCkiDFwTyXRpSqLI8hedfMQxK17YR4Cepv+SnmBHl3invwsUSLlkvSs3dbZUkXoO+2UOekMz5APH4 Aw4qkuEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNROz-00B3Y1-1I; Mon, 15 Aug 2022 04:08:33 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNROw-00B3Wi-ET; Mon, 15 Aug 2022 04:08:31 +0000 X-UUID: 4d5db04eff8549bd85a6245ecb14ef57-20220814 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=b3BKeHNHkOmEyqFXi/2yjYXaBJc1kL89uDBD+OeJTSI=; b=FEkmgW+Tm+Z5rpzFAj5lHynf30gk1rKZY88eZGbiRemveQio9l99OrgUS0/lOH4vVZiFpNVuJ8tHO5/3o1z/QHPQD+2VzS1i8UWvJOrQNc+m/MI06z2I3DUo/Xoupjfb2vDcmB0cenrzhEsAaLXA24MqVRcfVQoxt47J20CRy6E=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.9,REQID:1af19278-9cd5-4525-bece-5ebdbd00fef4,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_H am,ACTION:release,TS:5 X-CID-META: VersionHash:3d8acc9,CLOUDID:24d4ceae-9535-44a6-aa9b-7f62b79b6ff6,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File: nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 4d5db04eff8549bd85a6245ecb14ef57-20220814 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1258734093; Sun, 14 Aug 2022 21:08:25 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 15 Aug 2022 11:07:47 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 15 Aug 2022 11:07:46 +0800 From: Yongqiang Niu To: Chun-Kuang Hu CC: Jassi Brar , Matthias Brugger , , , , , Hsin-Yi Wang , Yongqiang Niu , Allen-kh Cheng Subject: [PATCH v1, 1/1] mailbox: mtk-cmdq: fix gce timeout issue Date: Mon, 15 Aug 2022 11:07:40 +0800 Message-ID: <20220815030740.28899-2-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815030740.28899-1-yongqiang.niu@mediatek.com> References: <20220815030740.28899-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220814_210830_541980_B368AE29 X-CRM114-Status: GOOD ( 14.98 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Yongqiang Niu 1. enable gce ddr enable(gce reigster offset 0x48, bit 16 to 18) when gce work, and disable gce ddr enable when gce work job done 2. split cmdq clk enable/disable api, and control gce ddr enable/disable in clk enable/disable function to make sure it could protect when cmdq is multiple used by display and mdp Signed-off-by: Yongqiang Niu Signed-off-by: Allen-kh Cheng --- drivers/mailbox/mtk-cmdq-mailbox.c | 57 ++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 2578e5aaa935..64a47470f062 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -81,6 +81,8 @@ struct cmdq { u8 shift_pa; bool control_by_sw; u32 gce_num; + atomic_t usage; + spinlock_t lock; }; struct gce_plat { @@ -90,6 +92,46 @@ struct gce_plat { u32 gce_num; }; +static s32 cmdq_clk_enable(struct cmdq *cmdq) +{ + s32 usage, ret; + unsigned long flags; + + spin_lock_irqsave(&cmdq->lock, flags); + + usage = atomic_inc_return(&cmdq->usage); + + ret = clk_bulk_enable(cmdq->gce_num, cmdq->clocks); + if (usage <=0 || ret < 0) { + dev_err(cmdq->mbox.dev, "ref count %d ret %d suspend %d\n", + usage, ret, cmdq->suspended); + } else if (usage == 1) { + if (cmdq->control_by_sw) + writel((0x7 << 16) + 0x7, cmdq->base + GCE_GCTL_VALUE); + } + + spin_unlock_irqrestore(&cmdq->lock, flags); + + return ret; +} + +static void cmdq_clk_disable(struct cmdq *cmdq) +{ + s32 usage; + + usage = atomic_dec_return(&cmdq->usage); + + if (usage < 0) { + dev_err(cmdq->mbox.dev, "ref count %d suspend %d\n", + usage, cmdq->suspended); + } else if (usage == 0) { + if (cmdq->control_by_sw) + writel(0x7, cmdq->base + GCE_GCTL_VALUE); + } + + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); +} + u8 cmdq_get_shift_pa(struct mbox_chan *chan) { struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); @@ -271,7 +313,8 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq, if (list_empty(&thread->task_busy_list)) { cmdq_thread_disable(cmdq, thread); - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); + + cmdq_clk_disable(cmdq); } } @@ -360,8 +403,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) task->pkt = pkt; if (list_empty(&thread->task_busy_list)) { - WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); - + WARN_ON(cmdq_clk_enable(cmdq) < 0); /* * The thread reset will clear thread related register to 0, * including pc, end, priority, irq, suspend and enable. Thus @@ -433,7 +475,7 @@ static void cmdq_mbox_shutdown(struct mbox_chan *chan) } cmdq_thread_disable(cmdq, thread); - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); + cmdq_clk_disable(cmdq); done: /* @@ -479,7 +521,8 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) cmdq_thread_resume(thread); cmdq_thread_disable(cmdq, thread); - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); + + cmdq_clk_disable(cmdq); out: spin_unlock_irqrestore(&thread->chan->lock, flags); @@ -490,7 +533,8 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) spin_unlock_irqrestore(&thread->chan->lock, flags); if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK, enable, enable == 0, 1, timeout)) { - dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n", + dev_err(cmdq->mbox.dev, + "Fail to wait GCE thread 0x%x done\n", (u32)(thread->base - cmdq->base)); return -EFAULT; @@ -626,6 +670,7 @@ static int cmdq_probe(struct platform_device *pdev) WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); + spin_lock_init(&cmdq->lock); cmdq_init(cmdq); return 0;