| Message ID | 20220820224538.59489-2-lynxis@fe80.eu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: mediatek: sgmii: add support to change interface parameter while running | expand |
Hello, On Sun, 2022-08-21 at 00:45 +0200, Alexander Couzens wrote: > There are cases when the SGMII_PHYA_PWD register contains 0x9 which > prevents SGMII from working. The SGMII still shows link but no traffic > can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was > taken from a good working state of the SGMII interface. do you have access to register documentation? what does 0x9 actually mean? is the '0' value based on just empirical evaluation? Thanks! Paolo
Hi Paolo, > On Sun, 2022-08-21 at 00:45 +0200, Alexander Couzens wrote: > > There are cases when the SGMII_PHYA_PWD register contains 0x9 which > > prevents SGMII from working. The SGMII still shows link but no > > traffic can flow. Writing 0x0 to the PHYA_PWD register fix the > > issue. 0x0 was taken from a good working state of the SGMII > > interface. > > do you have access to register documentation? what does 0x9 actually > mean? is the '0' value based on just empirical evaluation? I don't have any documentation which describes 0x9. The datasheet [1] only contains the PHYA_PWD (0x10) bit and the initial value is 0x10. 0x0 value is based on a register readout without the patch from a working state. I've tested it on mt7622 and Daniel Golle on mt7986. [1] MT7622 Reference Manual, v1.0, 2018-12-19, 1972 pages Best, lynxis
diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c index 736839c84130..a01bb20ea957 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -36,9 +36,7 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) val |= SGMII_AN_RESTART; regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); - regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); - val &= ~SGMII_PHYA_PWD; - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); return 0; @@ -70,9 +68,7 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs, regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); /* Release PHYA power down state */ - regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); - val &= ~SGMII_PHYA_PWD; - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); return 0; }
There are cases when the SGMII_PHYA_PWD register contains 0x9 which prevents SGMII from working. The SGMII still shows link but no traffic can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was taken from a good working state of the SGMII interface. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)