| Message ID | 20220829080830.5378-3-chunfeng.yun@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/7] dt-bindings: phy: mediatek,tphy: add support type of SGMII | expand |
Il 29/08/22 10:08, Chunfeng Yun ha scritto: > Add a property to set usb2 phy's pre-emphasis, it's disabled by default > on some SoCs. > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > --- > v2: no changes > --- > drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c > index 8ee7682b8e93..986fde0f63a0 100644 > --- a/drivers/phy/mediatek/phy-mtk-tphy.c > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c > @@ -72,6 +72,8 @@ > #define PA5_RG_U2_HS_100U_U3_EN BIT(11) > > #define U3P_USBPHYACR6 0x018 > +#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) > +#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) Hello Chunfeng, can you please clarify which SoC is this change referred to? If I'm not missing anything, there may be a register layout conflict between one version and the other for T-PHYs, for which, it may be a good idea to add a PHY version check before allowing to write settings that are supported only on a specific IP... Regards, Angelo
On Wed, 2022-08-31 at 10:14 +0200, AngeloGioacchino Del Regno wrote: > Il 29/08/22 10:08, Chunfeng Yun ha scritto: > > Add a property to set usb2 phy's pre-emphasis, it's disabled by > > default > > on some SoCs. > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > --- > > v2: no changes > > --- > > drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c > > b/drivers/phy/mediatek/phy-mtk-tphy.c > > index 8ee7682b8e93..986fde0f63a0 100644 > > --- a/drivers/phy/mediatek/phy-mtk-tphy.c > > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c > > @@ -72,6 +72,8 @@ > > #define PA5_RG_U2_HS_100U_U3_EN BIT(11) > > > > #define U3P_USBPHYACR6 0x018 > > +#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) > > +#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) > > Hello Chunfeng, > > can you please clarify which SoC is this change referred to? These bits are reserved before using 12nm process. > > If I'm not missing anything, there may be a register layout conflict As I know these reserved bits are not used before, but now used to tune pre-emphasis after supporting 12nm or 5nm process. > between > one version and the other for T-PHYs, for which, it may be a good > idea to add > a PHY version check before allowing to write settings that are > supported only > on a specific IP... Do you know which SoC used bits, I can confirm it with our DE. Thanks a lot > > Regards, > Angelo >
Il 08/09/22 03:39, Chunfeng Yun ha scritto: > On Wed, 2022-08-31 at 10:14 +0200, AngeloGioacchino Del Regno wrote: >> Il 29/08/22 10:08, Chunfeng Yun ha scritto: >>> Add a property to set usb2 phy's pre-emphasis, it's disabled by >>> default >>> on some SoCs. >>> >>> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> >>> --- >>> v2: no changes >>> --- >>> drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++ >>> 1 file changed, 10 insertions(+) >>> >>> diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c >>> b/drivers/phy/mediatek/phy-mtk-tphy.c >>> index 8ee7682b8e93..986fde0f63a0 100644 >>> --- a/drivers/phy/mediatek/phy-mtk-tphy.c >>> +++ b/drivers/phy/mediatek/phy-mtk-tphy.c >>> @@ -72,6 +72,8 @@ >>> #define PA5_RG_U2_HS_100U_U3_EN BIT(11) >>> >>> #define U3P_USBPHYACR6 0x018 >>> +#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) >>> +#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) >> >> Hello Chunfeng, >> >> can you please clarify which SoC is this change referred to? > These bits are reserved before using 12nm process. > >> >> If I'm not missing anything, there may be a register layout conflict > As I know these reserved bits are not used before, but now used to tune > pre-emphasis after supporting 12nm or 5nm process. > >> between >> one version and the other for T-PHYs, for which, it may be a good >> idea to add >> a PHY version check before allowing to write settings that are >> supported only >> on a specific IP... > Do you know which SoC used bits, I can confirm it with our DE. > MT8195, MT8186 (and others), RG_USB20_PHY_REV is marked as bit 31:24. Regards, Angelo
On Thu, 2022-09-08 at 10:05 +0200, AngeloGioacchino Del Regno wrote: > Il 08/09/22 03:39, Chunfeng Yun ha scritto: > > On Wed, 2022-08-31 at 10:14 +0200, AngeloGioacchino Del Regno > > wrote: > > > Il 29/08/22 10:08, Chunfeng Yun ha scritto: > > > > Add a property to set usb2 phy's pre-emphasis, it's disabled by > > > > default > > > > on some SoCs. > > > > > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > > > --- > > > > v2: no changes > > > > --- > > > > drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++ > > > > 1 file changed, 10 insertions(+) > > > > > > > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c > > > > b/drivers/phy/mediatek/phy-mtk-tphy.c > > > > index 8ee7682b8e93..986fde0f63a0 100644 > > > > --- a/drivers/phy/mediatek/phy-mtk-tphy.c > > > > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c > > > > @@ -72,6 +72,8 @@ > > > > #define PA5_RG_U2_HS_100U_U3_EN BIT(11) > > > > > > > > #define U3P_USBPHYACR6 0x018 > > > > +#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) > > > > +#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) > > > > > > Hello Chunfeng, > > > > > > can you please clarify which SoC is this change referred to? > > > > These bits are reserved before using 12nm process. > > > > > > > > If I'm not missing anything, there may be a register layout > > > conflict > > > > As I know these reserved bits are not used before, but now used to > > tune > > pre-emphasis after supporting 12nm or 5nm process. > > > > > between > > > one version and the other for T-PHYs, for which, it may be a good > > > idea to add > > > a PHY version check before allowing to write settings that are > > > supported only > > > on a specific IP... > > > > Do you know which SoC used bits, I can confirm it with our DE. > > > > MT8195, MT8186 (and others), RG_USB20_PHY_REV is marked as bit 31:24. Sorry, there is something wrong, the register map is not updated; > > Regards, > Angelo >
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 8ee7682b8e93..986fde0f63a0 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -72,6 +72,8 @@ #define PA5_RG_U2_HS_100U_U3_EN BIT(11) #define U3P_USBPHYACR6 0x018 +#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) +#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) #define PA6_RG_U2_BC11_SW_EN BIT(23) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) #define PA6_RG_U2_DISCTH GENMASK(7, 4) @@ -370,6 +372,7 @@ struct mtk_phy_instance { int eye_term; int intr; int discth; + int pre_emphasis; bool bc12_en; }; @@ -841,10 +844,13 @@ static void phy_parse_property(struct mtk_tphy *tphy, &instance->intr); device_property_read_u32(dev, "mediatek,discth", &instance->discth); + device_property_read_u32(dev, "mediatek,pre-emphasis", + &instance->pre_emphasis); dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n", instance->bc12_en, instance->eye_src, instance->eye_vrt, instance->eye_term, instance->intr, instance->discth); + dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis); } static void u2_phy_props_set(struct mtk_tphy *tphy, @@ -875,6 +881,10 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, if (instance->discth) mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(instance->discth)); + + if (instance->pre_emphasis) + mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, + PA6_RG_U2_PRE_EMP_VAL(instance->pre_emphasis)); } /* type switch for usb3/pcie/sgmii/sata */
Add a property to set usb2 phy's pre-emphasis, it's disabled by default on some SoCs. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- v2: no changes --- drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++ 1 file changed, 10 insertions(+)