From patchwork Wed Aug 31 12:55:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chengci.Xu" X-Patchwork-Id: 12960742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1805FECAAD4 for ; Wed, 31 Aug 2022 13:56:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3HNsi4I/zvrgfKJEKRa6DtMAii/2wtR4D+Ys6srgA6k=; b=WBO2eRqSjnnobrhhW8lRWIShG2 NmZaxmxwHGPVe+KAm2Zd3gCPWdrxLXxgjfyZXRB3eF82BTwMsgZvbOb0bZXzsuDYBlf5rbGwPG/sp x1sDT48qfHhDKzQAxzgkRz858iCFtWM6MSGuZoCqcENQV/KtV33llmAqrWFF+TLmZw37fZF/X5XF0 tF7uq1jclJwB/Bpzo+vLLZ4LK++ZXYFJaoc/Z4+M1oxLV9c0QBpmlfq9bA2Cn9kGCz2oEDKSBu6gC TYITLY+sEoM7oXLH08tUQU1KEQNOcahaoJzKtBskUSOaQAEs1JD3PhfxoW2a/U+whWoLIVqKYDWbz 84hVbelg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTOCg-006UuJ-0D; Wed, 31 Aug 2022 13:56:26 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTOCS-006UpZ-Dl; Wed, 31 Aug 2022 13:56:13 +0000 X-UUID: c0f50d56324a4242bd35bcde80abe352-20220831 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3HNsi4I/zvrgfKJEKRa6DtMAii/2wtR4D+Ys6srgA6k=; b=XdfFOein8F3PckSzDqGFWlNwjXadMT8CogVk2H39cKqfxQbPOjoQz2ABg0owx/uo6QZk4Ty+1VXiTnDeRl2/74mAzrfIq8SBP2OpzXqkvaj+SSvY+MHHG5EO6QGmeX7glxEvJRTQj4Td+7cSUiueLjiGqfJIx9uouX4ZrCamL6s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:9f5272fb-941f-4e57-87fb-877018071622,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Releas e_Ham,ACTION:release,TS:-25 X-CID-META: VersionHash:84eae18,CLOUDID:10742956-e800-47dc-8adf-0c936acf4f1b,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: c0f50d56324a4242bd35bcde80abe352-20220831 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 238997370; Wed, 31 Aug 2022 06:56:07 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 31 Aug 2022 20:55:31 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 31 Aug 2022 20:55:30 +0800 From: Chengci.Xu To: Yong Wu , Joerg Roedel , "Will Deacon" , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Chengci.Xu Subject: [PATCH v2 2/3] iommu/mediatek: Add enable IOMMU SMC command for INFRA master Date: Wed, 31 Aug 2022 20:55:01 +0800 Message-ID: <20220831125502.7818-3-chengci.xu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220831125502.7818-1-chengci.xu@mediatek.com> References: <20220831125502.7818-1-chengci.xu@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220831_065612_480571_9CF653B5 X-CRM114-Status: GOOD ( 17.62 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The register which can enable IOMMU for INFRA master should be setted in secure world for security concerns. Therefore, we add a SMC command for INFRA master to enable/disable INFRA IOMMU in ATF. This function is prepared for MT8188. Signed-off-by: Chengci.Xu --- drivers/iommu/mtk_iommu.c | 34 ++++++++++++++++++++++++++-------- include/soc/mediatek/smi.h | 1 + 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7e363b1f24df..6fe780783ec8 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -3,6 +3,7 @@ * Copyright (c) 2015-2016 MediaTek Inc. * Author: Yong Wu */ +#include #include #include #include @@ -28,6 +29,7 @@ #include #include #include +#include #include #include @@ -138,6 +140,7 @@ #define PM_CLK_AO BIT(15) #define IFA_IOMMU_PCIE_SUPPORT BIT(16) #define PGTABLE_PA_35_EN BIT(17) +#define CFG_IFA_MASTER_IN_ATF BIT(18) #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) == (_x)) @@ -554,14 +557,29 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, else larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { - peri_mmuen_msk = BIT(portid); - /* PCI dev has only one output id, enable the next writing bit for PCIe */ - if (dev_is_pci(dev)) - peri_mmuen_msk |= BIT(portid + 1); - - peri_mmuen = enable ? peri_mmuen_msk : 0; - ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, - peri_mmuen_msk, peri_mmuen); + if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { + struct arm_smccc_res res; + + portid = MTK_M4U_TO_PORT(fwspec->ids[i]); + arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, + IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, + portid, enable, 0, 0, 0, 0, &res); + ret = (int)res.a0; + + } else { + peri_mmuen_msk = BIT(portid); + /* PCI dev has only one output id, + * enable the next writing bit for PCIe + */ + if (dev_is_pci(dev)) + peri_mmuen_msk |= BIT(portid + 1); + + peri_mmuen = enable ? peri_mmuen_msk : 0; + ret = regmap_update_bits(data->pericfg, + PERICFG_IOMMU_1, + peri_mmuen_msk, + peri_mmuen); + } if (ret) dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n", enable ? "enable" : "disable", diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h index dfd8efca5e60..99f13b0e416d 100644 --- a/include/soc/mediatek/smi.h +++ b/include/soc/mediatek/smi.h @@ -13,6 +13,7 @@ enum iommu_atf_cmd { IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */ + IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master en/disable iommu */ IOMMU_ATF_CMD_MAX, };