diff mbox series

[v2,3/3] iommu/mediatek: Add MT8188 IOMMU Support

Message ID 20220831125502.7818-4-chengci.xu@mediatek.com (mailing list archive)
State New, archived
Headers show
Series MT8188 IOMMU SUPPORT | expand

Commit Message

Chengci.Xu Aug. 31, 2022, 12:55 p.m. UTC 
MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other
is for vpp. and 1 INFRA IOMMU.

Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 48 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

Comments

AngeloGioacchino Del Regno Sept. 2, 2022, 9:04 a.m. UTC | #1 
Il 31/08/22 14:55, Chengci.Xu ha scritto:
> MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other
> is for vpp. and 1 INFRA IOMMU.
> 
> Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> ---
>   drivers/iommu/mtk_iommu.c | 48 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 48 insertions(+)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 6fe780783ec8..98c2eae5229e 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -164,6 +164,7 @@ enum mtk_iommu_plat {
>   	M4U_MT8173,
>   	M4U_MT8183,
>   	M4U_MT8186,
> +	M4U_MT8188,
>   	M4U_MT8192,
>   	M4U_MT8195,
>   };
> @@ -1479,6 +1480,50 @@ static const struct mtk_iommu_plat_data mt8186_data_mm = {
>   	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
>   };
>   
> +static const struct mtk_iommu_plat_data mt8188_data_infra = {
> +	.m4u_plat	  = M4U_MT8188,
> +	.flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
> +			    MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT |
> +			    CFG_IFA_MASTER_IN_ATF,
> +	.pericfg_comp_str = "mediatek,mt8188-pericfg_ao",

pericfg_comp_str is used only for IOMMU enable from Linux, but MT8188 enables it
with a SMC command, so this is unused.

Please drop it.

> +	.inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
> +	.banks_num	  = 1,
> +	.banks_enable     = {true},
> +	.iova_region      = single_domain,
> +	.iova_region_nr   = ARRAY_SIZE(single_domain),
> +};
> +

Regards,
Angelo
Chengci.Xu Sept. 8, 2022, 9:57 a.m. UTC | #2 
On Fri, 2022-09-02 at 11:04 +0200, AngeloGioacchino Del Regno wrote:
> Il 31/08/22 14:55, Chengci.Xu ha scritto:
> > MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the
> > other
> > is for vpp. and 1 INFRA IOMMU.
> > 
> > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> > ---
> >   drivers/iommu/mtk_iommu.c | 48
> > +++++++++++++++++++++++++++++++++++++++
> >   1 file changed, 48 insertions(+)
> > 
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index 6fe780783ec8..98c2eae5229e 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -164,6 +164,7 @@ enum mtk_iommu_plat {
> >   	M4U_MT8173,
> >   	M4U_MT8183,
> >   	M4U_MT8186,
> > +	M4U_MT8188,
> >   	M4U_MT8192,
> >   	M4U_MT8195,
> >   };
> > @@ -1479,6 +1480,50 @@ static const struct mtk_iommu_plat_data
> > mt8186_data_mm = {
> >   	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> >   };
> >   
> > +static const struct mtk_iommu_plat_data mt8188_data_infra = {
> > +	.m4u_plat	  = M4U_MT8188,
> > +	.flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE |
> > PM_CLK_AO |
> > +			    MTK_IOMMU_TYPE_INFRA |
> > IFA_IOMMU_PCIE_SUPPORT |
> > +			    CFG_IFA_MASTER_IN_ATF,
> > +	.pericfg_comp_str = "mediatek,mt8188-pericfg_ao",
> 
> pericfg_comp_str is used only for IOMMU enable from Linux, but MT8188
> enables it
> with a SMC command, so this is unused.
> 
> Please drop it.

Thanks for your review.

Yes. For MT8188, pericfg_comp_str is unused and should be dropped.
But deleting it simply will lead to INFRA IOMMU probe fail because
following code flow.

	line 1236:
		p = data->plat_data->pericfg_comp_str;
		data->pericfg = syscon_regmap_lookup_by_compatible(p);
		if (IS_ERR(data->pericfg)) {
			ret = PTR_ERR(data->pericfg);
			goto out_runtime_disable;
		}

So we will update probe flow(patch 2/3) and then drop it(patch 3/3) in
the next version. 

> 
> > +	.inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
> > +	.banks_num	  = 1,
> > +	.banks_enable     = {true},
> > +	.iova_region      = single_domain,
> > +	.iova_region_nr   = ARRAY_SIZE(single_domain),
> > +};
> > +
> 
> Regards,
> Angelo
> 
>
diff mbox series

Patch

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 6fe780783ec8..98c2eae5229e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -164,6 +164,7 @@  enum mtk_iommu_plat {
 	M4U_MT8173,
 	M4U_MT8183,
 	M4U_MT8186,
+	M4U_MT8188,
 	M4U_MT8192,
 	M4U_MT8195,
 };
@@ -1479,6 +1480,50 @@  static const struct mtk_iommu_plat_data mt8186_data_mm = {
 	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
 };
 
+static const struct mtk_iommu_plat_data mt8188_data_infra = {
+	.m4u_plat	  = M4U_MT8188,
+	.flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
+			    MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT |
+			    CFG_IFA_MASTER_IN_ATF,
+	.pericfg_comp_str = "mediatek,mt8188-pericfg_ao",
+	.inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
+	.banks_num	  = 1,
+	.banks_enable     = {true},
+	.iova_region      = single_domain,
+	.iova_region_nr   = ARRAY_SIZE(single_domain),
+};
+
+static const struct mtk_iommu_plat_data mt8188_data_vdo = {
+	.m4u_plat	= M4U_MT8188,
+	.flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
+			  WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
+	.hw_list        = &m4ulist,
+	.inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+	.banks_num      = 1,
+	.banks_enable   = {true},
+	.iova_region	= mt8192_multi_dom,
+	.iova_region_nr	= ARRAY_SIZE(mt8192_multi_dom),
+	.larbid_remap   = {{2}, {0}, {21}, {0}, {19}, {9, 10,
+			   11 /* 11a */, 25 /* 11c */},
+			   {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}},
+};
+
+static const struct mtk_iommu_plat_data mt8188_data_vpp = {
+	.m4u_plat	= M4U_MT8188,
+	.flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
+			  WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
+	.hw_list        = &m4ulist,
+	.inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+	.banks_num      = 1,
+	.banks_enable   = {true},
+	.iova_region	= mt8192_multi_dom,
+	.iova_region_nr	= ARRAY_SIZE(mt8192_multi_dom),
+	.larbid_remap   = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID},
+			   {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID,
+			   16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID,
+			   27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}},
+};
+
 static const struct mtk_iommu_plat_data mt8192_data = {
 	.m4u_plat       = M4U_MT8192,
 	.flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
@@ -1546,6 +1591,9 @@  static const struct of_device_id mtk_iommu_of_ids[] = {
 	{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
 	{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
 	{ .compatible = "mediatek,mt8186-iommu-mm",    .data = &mt8186_data_mm}, /* mm: m4u */
+	{ .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra},
+	{ .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo},
+	{ .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp},
 	{ .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
 	{ .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
 	{ .compatible = "mediatek,mt8195-iommu-vdo",   .data = &mt8195_data_vdo},