| Message ID | 20220909073726.32423-1-aouledameur@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | thermal: mediatek: Add support for MT8365 SoC | expand |
Il 09/09/22 09:37, Amjad Ouled-Ameur ha scritto: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > Add logic in order to be able to turn on the control buffer on MT8365. > This change now allows to have control buffer support for MTK_THERMAL_V1, > and it allows to define the register offset, and mask used to enable it. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Fabien Parent <fparent@baylibre.com> > Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Hello Amjad, I agree with these changes, but I can't give you my R-b tag: this driver has been moved to drivers/thermal/mediatek/soc_temp.c and, as a result, this series cannot be applied. Please rebase. Regards, Angelo
Il 09/09/22 09:37, Amjad Ouled-Ameur ha scritto: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > Add logic in order to be able to turn on the control buffer on MT8365. > This change now allows to have control buffer support for MTK_THERMAL_V1, > and it allows to define the register offset, and mask used to enable it. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Fabien Parent <fparent@baylibre.com> > Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Sorry for the previous reply. I got confused by a local tree. The driver is there upstream. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index 8440692e3890..d8ddceb75372 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -271,6 +271,9 @@ struct mtk_thermal_data { bool need_switch_bank; struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; enum mtk_thermal_version version; + u32 apmixed_buffer_ctl_reg; + u32 apmixed_buffer_ctl_mask; + u32 apmixed_buffer_ctl_set; }; struct mtk_thermal { @@ -514,6 +517,9 @@ static const struct mtk_thermal_data mt7622_thermal_data = { .adcpnp = mt7622_adcpnp, .sensor_mux_values = mt7622_mux_values, .version = MTK_THERMAL_V2, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, + .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), + .apmixed_buffer_ctl_set = BIT(0), }; /* @@ -963,14 +969,18 @@ static const struct of_device_id mtk_thermal_of_match[] = { }; MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); -static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) +static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, + void __iomem *apmixed_base) { - int tmp; + u32 tmp; + + if (!mt->conf->apmixed_buffer_ctl_reg) + return; - tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); - tmp &= ~(0x37); - tmp |= 0x1; - writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); + tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg); + tmp &= mt->conf->apmixed_buffer_ctl_mask; + tmp |= mt->conf->apmixed_buffer_ctl_set; + writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg); udelay(200); } @@ -1070,8 +1080,9 @@ static int mtk_thermal_probe(struct platform_device *pdev) goto err_disable_clk_auxadc; } + mtk_thermal_turn_on_buffer(mt, apmixed_base); + if (mt->conf->version == MTK_THERMAL_V2) { - mtk_thermal_turn_on_buffer(apmixed_base); mtk_thermal_release_periodic_ts(mt, auxadc_base); }