| Message ID | 20220913122428.374280-3-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek Helio X10 MT6795 - M4U/IOMMU Support | expand |
On 13/09/2022 14:24, AngeloGioacchino Del Regno wrote: > In preparation for adding support for MT6795, add a new flag named > TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat > type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat > checks there in the future. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Reviewed-by: Yong Wu <yong.wu@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 6 ++++-- > drivers/memory/mtk-smi.c | 1 + > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 7e363b1f24df..b511359376f4 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -138,6 +138,7 @@ > #define PM_CLK_AO BIT(15) > #define IFA_IOMMU_PCIE_SUPPORT BIT(16) > #define PGTABLE_PA_35_EN BIT(17) > +#define TF_PORT_TO_ADDR_MT8173 BIT(18) > > #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ > ((((pdata)->flags) & (mask)) == (_x)) > @@ -955,7 +956,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int ban > * Global control settings are in bank0. May re-init these global registers > * since no sure if there is bank0 consumers. > */ > - if (data->plat_data->m4u_plat == M4U_MT8173) { > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { > regval = F_MMU_PREFETCH_RT_REPLACE_MOD | > F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; > } else { > @@ -1427,7 +1428,8 @@ static const struct mtk_iommu_plat_data mt8167_data = { > static const struct mtk_iommu_plat_data mt8173_data = { > .m4u_plat = M4U_MT8173, > .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | > - HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, > + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | > + TF_PORT_TO_ADDR_MT8173, > .inv_sel_reg = REG_MMU_INV_SEL_GEN1, > .banks_num = 1, > .banks_enable = {true}, > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index 5a9754442bc7..cd415ed1f4ca 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -462,6 +462,7 @@ static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) > if (ret) { > /* TODO: Reset this larb if it fails here. */ > dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); > + ret = -EAGAIN; Doesn't look related nor explained in commit msg. Best regards, Krzysztof
Il 13/09/22 16:00, Krzysztof Kozlowski ha scritto: > On 13/09/2022 14:24, AngeloGioacchino Del Regno wrote: >> In preparation for adding support for MT6795, add a new flag named >> TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat >> type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat >> checks there in the future. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> Reviewed-by: Yong Wu <yong.wu@mediatek.com> >> --- >> drivers/iommu/mtk_iommu.c | 6 ++++-- >> drivers/memory/mtk-smi.c | 1 + >> 2 files changed, 5 insertions(+), 2 deletions(-) ..snip.. >> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c >> index 5a9754442bc7..cd415ed1f4ca 100644 >> --- a/drivers/memory/mtk-smi.c >> +++ b/drivers/memory/mtk-smi.c >> @@ -462,6 +462,7 @@ static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) >> if (ret) { >> /* TODO: Reset this larb if it fails here. */ >> dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); >> + ret = -EAGAIN; > > Doesn't look related nor explained in commit msg. This is because it's not related.. not explained... and embarassing, as something went wrong during the rebase. Many thanks for pinging me about that, I'm immediately sending a new version. Regards, Angelo
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7e363b1f24df..b511359376f4 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -138,6 +138,7 @@ #define PM_CLK_AO BIT(15) #define IFA_IOMMU_PCIE_SUPPORT BIT(16) #define PGTABLE_PA_35_EN BIT(17) +#define TF_PORT_TO_ADDR_MT8173 BIT(18) #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) == (_x)) @@ -955,7 +956,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int ban * Global control settings are in bank0. May re-init these global registers * since no sure if there is bank0 consumers. */ - if (data->plat_data->m4u_plat == M4U_MT8173) { + if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { regval = F_MMU_PREFETCH_RT_REPLACE_MOD | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; } else { @@ -1427,7 +1428,8 @@ static const struct mtk_iommu_plat_data mt8167_data = { static const struct mtk_iommu_plat_data mt8173_data = { .m4u_plat = M4U_MT8173, .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | - HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | + TF_PORT_TO_ADDR_MT8173, .inv_sel_reg = REG_MMU_INV_SEL_GEN1, .banks_num = 1, .banks_enable = {true}, diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 5a9754442bc7..cd415ed1f4ca 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -462,6 +462,7 @@ static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) if (ret) { /* TODO: Reset this larb if it fails here. */ dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); + ret = -EAGAIN; } return ret; }