From patchwork Mon Sep 19 08:26:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chengci.Xu" X-Patchwork-Id: 12979763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A146C54EE9 for ; Mon, 19 Sep 2022 08:28:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=LTZNciyBkNwy95/RoMBu6/ycwdKscgUxR6iM9crgHfo=; b=mPtRjtRLk2EoDRaihrPQ8EQi7G HXTFo8J14aJmtiYujrxUDCjkKF6oW8luugzx7TuErtZjr01L/Xzy0EKBB3bdh2yD564AHyKC7VQbd VcIyGJ5QkVjgLZsW3MBlk9l32MvFk7umoOr/F8Wf9+zcbEuOBfAt+cMwFJWm6CPeFC3LLYoYU7Bcx fy+XQy3zBvL+IzB7E9Muo172CNc7fWiJZ7kUiW2ahvxUuzZcr81VvFEutmnzM1A3JkHvSi7M1fzra +CwBG8Q6kcOatlZbeMZF5nbmUJTEzqtkmbs1WsPdPyJhySx9GR1mLLG+FJw+lPooV1I25lQeSKn07 9yvKpA7A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oaC8Q-00A32P-5c; Mon, 19 Sep 2022 08:28:10 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oaC7I-00A2KB-QO; Mon, 19 Sep 2022 08:27:07 +0000 X-UUID: 19dcc60bdece40188402c15e9c89b016-20220919 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LTZNciyBkNwy95/RoMBu6/ycwdKscgUxR6iM9crgHfo=; b=tZwORYVvEqHuJsDoWLAfwAdpea36F5JDMu9JSH7+P9K6QXd0j+ONNAxi4xwJ8zsSbNuf+EOPzCDA/epwdyqNwYyiJ5TcW2bgASiAw+NEsPCun/1SKBErCn6F7qKQhqHmgg45yCXQRTpGxssK9+czjJfYlcBvTh6B1lEc77Rv3Qk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:555de5db-eef9-4c44-a359-ca4cd141777e,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:d878e0f6-6e85-48d9-afd8-0504bbfe04cb,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 19dcc60bdece40188402c15e9c89b016-20220919 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 872890944; Mon, 19 Sep 2022 01:26:54 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 19 Sep 2022 16:26:41 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 19 Sep 2022 16:26:40 +0800 From: Chengci.Xu To: Yong Wu , Joerg Roedel , "Will Deacon" , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Chengci.Xu Subject: [PATCH v3 2/3] iommu/mediatek: Add enable IOMMU SMC command for INFRA master Date: Mon, 19 Sep 2022 16:26:10 +0800 Message-ID: <20220919082611.19824-3-chengci.xu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220919082611.19824-1-chengci.xu@mediatek.com> References: <20220919082611.19824-1-chengci.xu@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220919_012700_895712_69B0A38A X-CRM114-Status: GOOD ( 15.80 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The register which can enable IOMMU for INFRA master should be setted in secure world for security concerns. Therefore, we add a SMC command for INFRA master to enable/disable INFRA IOMMU in ATF. This function is prepared for MT8188. Signed-off-by: Chengci.Xu --- drivers/iommu/mtk_iommu.c | 21 +++++++++++++++++++-- include/soc/mediatek/smi.h | 1 + 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 552e4eb8c610..8b8a289bab2c 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -3,6 +3,7 @@ * Copyright (c) 2015-2016 MediaTek Inc. * Author: Yong Wu */ +#include #include #include #include @@ -28,6 +29,7 @@ #include #include #include +#include #include #include @@ -138,6 +140,7 @@ #define PM_CLK_AO BIT(15) #define IFA_IOMMU_PCIE_SUPPORT BIT(16) #define PGTABLE_PA_35_EN BIT(17) +#define CFG_IFA_MASTER_IN_ATF BIT(18) #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) == (_x)) @@ -553,7 +556,20 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); else larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); - } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { + } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && + MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, + IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, + portid, enable, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + dev_err(dev, "%s iommu(%s) inframaster %d fail(%ld).\n", + enable ? "enable" : "disable", + dev_name(data->dev), portid, res.a0); + ret = -EINVAL; + } + } else { peri_mmuen_msk = BIT(portid); /* PCI dev has only one output id, enable the next writing bit for PCIe */ if (dev_is_pci(dev)) @@ -1213,7 +1229,8 @@ static int mtk_iommu_probe(struct platform_device *pdev) dev_err_probe(dev, ret, "mm dts parse fail\n"); goto out_runtime_disable; } - } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { + } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && + !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { p = data->plat_data->pericfg_comp_str; data->pericfg = syscon_regmap_lookup_by_compatible(p); if (IS_ERR(data->pericfg)) { diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h index dfd8efca5e60..99f13b0e416d 100644 --- a/include/soc/mediatek/smi.h +++ b/include/soc/mediatek/smi.h @@ -13,6 +13,7 @@ enum iommu_atf_cmd { IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */ + IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master en/disable iommu */ IOMMU_ATF_CMD_MAX, };