From patchwork Wed Sep 21 09:14:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 12983482 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8279C32771 for ; Wed, 21 Sep 2022 09:20:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1BA6hiIvwWDL5vTuKacqUcaZbBf6nFqU9YqypFBBIwo=; b=bBSEEuA2cAhmpL48lT3n4Lz7BH bG+5Vb2nP/eijA4lotjB0ErTJkbC8wjbAPFd7F2xpJPa35tBNFFPh/n75rYozNv+LO4WRTimc4UdT TDwf2xQ5ww8Tn7o+2Gstyh9pGj2HAOuN08C6AyhXQxS5sGL2m+9LJe/SCmHF2y7SPHXJ2Vz/+bnWC Hpu4+TXn0rDezxyMpEUHXLzHJlrlKFb2yJnIOUvnH0igjHu64I0j9wQjlfwH+pfRIQ4ol5JN75bkn ogZs1/4uEtCKjLeZY4BUZ1r02fWwVBOlNpYD8H+wpK3YOt4hIcqyax2T9U4iTHsVtJFoW1Cll0HN0 ZQ0H5oNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oavty-00AL4T-OJ; Wed, 21 Sep 2022 09:20:18 +0000 Received: from madras.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e5ab]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oavp6-00AIm8-7s; Wed, 21 Sep 2022 09:15:23 +0000 Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 93C706602003; Wed, 21 Sep 2022 10:15:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1663751714; bh=OaDL1DMQnLuEb+lZMWqNDRbICAW6fIhIyoRCPrkCYEQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MzKEpa23JAc6Aqil5oy704Os6IIDrkhG8vH8HPwHn/jwxRfIkEesPn/RTImFOb7qP 2aI3DfSiH/MXLnPNmKvbKzb1q9oB437C+fT9KzvbL9dIxqZVw7WsW3kn0UTEhv0O4/ I6Tvesi8G2fuWWUzSa3628mozExvDnA1cP7fnuSrLTxPBD21gdMC8OhEC9QIp3eizm Bg5aYZ8AoOuaoOBgic4wgD//qRbTQZhjy8UAFzA0Zd7ZgNh4z+QT7LceeoPgW5E0JC ONcTPnaCeqD0AGliXIwkZ5bLBeLpih5+Yz7z+WvgAGMplvdnnoiQPkQ01n/okcF/T5 fvYhp9R+u7iLg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, y.oudjana@protonmail.com, angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, ck.hu@mediatek.com, fparent@baylibre.com, rex-bc.chen@mediatek.com, tinghan.shen@mediatek.com, ikjn@chromium.org, miles.chen@mediatek.com, sam.shih@mediatek.com, wenst@chromium.org, bgolaszewski@baylibre.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, kernel@collabora.com, Rob Herring Subject: [RESEND PATCH v6 3/8] dt-bindings: reset: Add bindings for MT6795 Helio X10 reset controllers Date: Wed, 21 Sep 2022 11:14:50 +0200 Message-Id: <20220921091455.41327-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220921091455.41327-1-angelogioacchino.delregno@collabora.com> References: <20220921091455.41327-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220921_021516_465661_57727523 X-CRM114-Status: GOOD ( 11.36 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add the reset controller bindings for MT6795. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- .../reset/mediatek,mt6795-resets.h | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt6795-resets.h diff --git a/include/dt-bindings/reset/mediatek,mt6795-resets.h b/include/dt-bindings/reset/mediatek,mt6795-resets.h new file mode 100644 index 000000000000..5464a4a79a70 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6795-resets.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6795 +#define _DT_BINDINGS_RESET_CONTROLLER_MT6795 + +/* INFRACFG resets */ +#define MT6795_INFRA_RST0_SCPSYS_RST 0 +#define MT6795_INFRA_RST0_PMIC_WRAP_RST 1 +#define MT6795_INFRA_RST1_MIPI_DSI_RST 2 +#define MT6795_INFRA_RST1_MIPI_CSI_RST 3 +#define MT6795_INFRA_RST1_MM_IOMMU_RST 4 + +/* MMSYS resets */ +#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 1 +#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 4 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 5 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 6 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 7 +#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 8 +#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 9 +#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 10 +#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 11 +#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 12 +#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 13 + +/* PERICFG resets */ +#define MT6795_PERI_NFI_SW_RST 0 +#define MT6795_PERI_THERM_SW_RST 1 +#define MT6795_PERI_MSDC1_SW_RST 2 + +/* TOPRGU resets */ +#define MT6795_TOPRGU_INFRA_SW_RST 0 +#define MT6795_TOPRGU_MM_SW_RST 1 +#define MT6795_TOPRGU_MFG_SW_RST 2 +#define MT6795_TOPRGU_VENC_SW_RST 3 +#define MT6795_TOPRGU_VDEC_SW_RST 4 +#define MT6795_TOPRGU_IMG_SW_RST 5 +#define MT6795_TOPRGU_DDRPHY_SW_RST 6 +#define MT6795_TOPRGU_MD_SW_RST 7 +#define MT6795_TOPRGU_INFRA_AO_SW_RST 8 +#define MT6795_TOPRGU_MD_LITE_SW_RST 9 +#define MT6795_TOPRGU_APMIXED_SW_RST 10 +#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 11 +#define MT6795_TOPRGU_SW_RST_NUM 12 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */