| Message ID | 20221017142007.5408-2-mengqi.zhang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek eMMC inline encryption support | expand |
Il 17/10/22 16:20, Mengqi Zhang ha scritto: > add crypto clock control and ungate it before CQHCI init. > > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com> Hello Mengqi, I'm a bit surprised that enabling ICE only requires enabling a clock as on downstream code I see some SMC calls to MTK_SIP_KERNEL_HW_FDE_MSDC_CTL. Can you please explain why SMC calls are not needed here? Thanks, Angelo
On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote: > Il 17/10/22 16:20, Mengqi Zhang ha scritto: > > add crypto clock control and ungate it before CQHCI init. > > > > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com> > > Hello Mengqi, > I'm a bit surprised that enabling ICE only requires enabling a clock > as > on downstream code I see some SMC calls to > MTK_SIP_KERNEL_HW_FDE_MSDC_CTL. > > Can you please explain why SMC calls are not needed here? > > Thanks, > Angelo > Hi Angelo, > > In some MTK SoCs, we need set a encrypto enable bit > MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to > finish it. > But not every MTK SoC need to set this bit in secure world. This > patch is for these SoCs. > As for SMC call, we haven't found a proper way to deal with it, we'll > do it later. > > Thanks, > Mengqi.Zhang >
On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote: > Il 17/10/22 16:20, Mengqi Zhang ha scritto: > > add crypto clock control and ungate it before CQHCI init. > > > > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com> > > Hello Mengqi, > I'm a bit surprised that enabling ICE only requires enabling a clock > as > on downstream code I see some SMC calls to > MTK_SIP_KERNEL_HW_FDE_MSDC_CTL. > > Can you please explain why SMC calls are not needed here? > > Thanks, > Angelo > Hi Angelo, There are many wrong quotes in previous reply, let me fix it here. In some MTK SoC, we need set a encrypto enable bit MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to finish it. But not every MTK SoC need to set this bit in secure world. This patch is for these SoCs. As for SMC call, we haven't found a proper way to deal with it, we'll do it later. Thanks, Mengqi.Zhang
Il 31/10/22 10:50, Mengqi Zhang (张梦琦) ha scritto: > On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote: >> Il 17/10/22 16:20, Mengqi Zhang ha scritto: >>> add crypto clock control and ungate it before CQHCI init. >>> >>> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com> >> >> Hello Mengqi, >> I'm a bit surprised that enabling ICE only requires enabling a clock >> as >> on downstream code I see some SMC calls to >> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL. >> >> Can you please explain why SMC calls are not needed here? >> >> Thanks, >> Angelo >> > > Hi Angelo, > > There are many wrong quotes in previous reply, let me fix it here. > > In some MTK SoC, we need set a encrypto enable bit > MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to > finish it. > But not every MTK SoC need to set this bit in secure world. This patch > is for these SoCs. > As for SMC call, we haven't found a proper way to deal with it, we'll > do it later. > Thanks for clarifying. In that case, I'm a little worried about people trying to enable ICE on SoCs that do require calling into TZ and getting a crash... but it's anyway out of scope for this series, so: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 69d78604d1fc..8b6ef8691e5b 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -452,6 +452,7 @@ struct msdc_host { struct clk *bus_clk; /* bus clock which used to access register */ struct clk *src_clk_cg; /* msdc source clock control gate */ struct clk *sys_clk_cg; /* msdc subsys clock control gate */ + struct clk *crypto_clk; /* msdc crypto clock control gate */ struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; u32 mclk; /* mmc subsystem clock frequency */ u32 src_clk_freq; /* source clock frequency */ @@ -811,6 +812,7 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) static void msdc_gate_clock(struct msdc_host *host) { clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); + clk_disable_unprepare(host->crypto_clk); clk_disable_unprepare(host->src_clk_cg); clk_disable_unprepare(host->src_clk); clk_disable_unprepare(host->bus_clk); @@ -826,6 +828,7 @@ static int msdc_ungate_clock(struct msdc_host *host) clk_prepare_enable(host->bus_clk); clk_prepare_enable(host->src_clk); clk_prepare_enable(host->src_clk_cg); + clk_prepare_enable(host->crypto_clk); ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); if (ret) { dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); @@ -2643,6 +2646,15 @@ static int msdc_drv_probe(struct platform_device *pdev) goto host_free; } + /* only eMMC has crypto property */ + if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { + host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); + if (IS_ERR(host->crypto_clk)) + host->crypto_clk = NULL; + else + mmc->caps2 |= MMC_CAP2_CRYPTO; + } + host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { ret = -EINVAL;
add crypto clock control and ungate it before CQHCI init. Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)