From patchwork Sat Oct 22 09:05:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 13015874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06239C433FE for ; Sat, 22 Oct 2022 09:07:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UTXQqkN1u8oqr164Wn8zlXyUh6Ah1bcisEKsdbq/R2I=; b=KND80AsrwjggzH Yd4q4FWqdJZjW9Tws7P+ZAIV5/iOeJ4qW6er2JiGEBW0LhkUkIuDMzR55jT1b6n41GNlAX1zcefy/ TCY8mJ34U6VpgLgLyT86Z8hBWIGbXXF/v5vCyXgwBQipPQfli2GOXbd6zKLUUXq9APCJXsb4moBbt GI8y39np/gd3QfSvyV0F6rxT9Ytn+StpOZUuEtyJQ+goJgZoir/+yfkkL2EjdGNe0YA4PCeaZRX/C HYSb13A8mPFzJCqYDzkEFWA7Gp81+qTD7qRCXmWcbx2sD8fZ23HBF42Jp/793zIHShxlisO0wFEd1 iGXyF0ED0z82r7CS50zw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1omASy-00BtVJ-JG; Sat, 22 Oct 2022 09:06:52 +0000 Received: from mxout4.routing.net ([2a03:2900:1:a::9]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1omARp-00Bsxn-TG; Sat, 22 Oct 2022 09:05:44 +0000 Received: from mxbox1.masterlogin.de (unknown [192.168.10.88]) by mxout4.routing.net (Postfix) with ESMTP id 257011004AC; Sat, 22 Oct 2022 09:05:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1666429539; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UTXQqkN1u8oqr164Wn8zlXyUh6Ah1bcisEKsdbq/R2I=; b=SmTfGSC6OXmd26oEoU/Ks0TYmuRkykE3o3IR4gqyI+uXwtByG8LUFHpHGuf+C8MKNTgtf2 M7s/amoCv4ZMrFagV0HaGW086ciJ9xvZtlUz0g/sZNHXxjAIF8u3kfPAhUP0Mg9H5kd2yX ScjHxgUEFMUkxxcc0RPb32Av44N0krw= Received: from frank-G5.. (fttx-pool-80.245.73.148.bambit.de [80.245.73.148]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id 59F5C407B2; Sat, 22 Oct 2022 09:05:38 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Subject: [PATCH v2 3/5] dt-bindings: mmc: mtk-sd: Set clocks based on compatible Date: Sat, 22 Oct 2022 11:05:28 +0200 Message-Id: <20221022090530.16265-4-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221022090530.16265-1-linux@fw-web.de> References: <20221022090530.16265-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: eb8f1813-330d-417e-9bcc-0cc0defb3966 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221022_020542_260997_8493A632 X-CRM114-Status: GOOD ( 11.66 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Wenbin Mei , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Matthias Brugger , Chaotian Jing Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Nícolas F. R. A. Prado The binding was describing a single clock list for all platforms, but that's not really suitable: mt2712 requires an extra 'bus_clk' on some of its controllers, while mt8192 requires four different extra clocks. The rest of the platforms can share the same 3 clocks, with the third being optional as it's not present on all platforms. Move the clock definitions inside if blocks that match on the compatibles. In practice this gets rid of dtbs_check warnings on mt8192, since the 'bus_clk' clock from mt2712 is no longer expected on this platform. Fixes: 59a23395d8aa ("dt-bindings: mmc: Add support for MT8192 SoC") Signed-off-by: Nícolas F. R. A. Prado Signed-off-by: Frank Wunderlich --- .../devicetree/bindings/mmc/mtk-sd.yaml | 111 +++++++++++++----- 1 file changed, 81 insertions(+), 30 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 3cbf0208f1b4..c7bcf0c3dd5d 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -10,9 +10,6 @@ maintainers: - Chaotian Jing - Wenbin Mei -allOf: - - $ref: mmc-controller.yaml# - properties: compatible: oneOf: @@ -49,27 +46,11 @@ properties: description: Should contain phandle for the clock feeding the MMC controller. minItems: 2 - items: - - description: source clock (required). - - description: HCLK which used for host (required). - - description: independent source clock gate (required for MT2712). - - description: bus clock used for internal register access (required for MT2712 MSDC0/3). - - description: msdc subsys clock gate (required for MT8192). - - description: peripheral bus clock gate (required for MT8192). - - description: AXI bus clock gate (required for MT8192). - - description: AHB bus clock gate (required for MT8192). + maxItems: 7 clock-names: minItems: 2 - items: - - const: source - - const: hclk - - const: source_cg - - const: bus_clk - - const: sys_cg - - const: pclk_cg - - const: axi_cg - - const: ahb_cg + maxItems: 7 interrupts: description: @@ -191,15 +172,85 @@ required: - vmmc-supply - vqmmc-supply -if: - properties: - compatible: - contains: - const: mediatek,mt8183-mmc -then: - properties: - reg: - minItems: 2 +allOf: + - $ref: mmc-controller.yaml# + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-mmc + then: + properties: + reg: + minItems: 2 + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-mmc + then: + properties: + clocks: + items: + - description: source clock + - description: HCLK which used for host + - description: independent source clock gate + - description: msdc subsys clock gate + - description: peripheral bus clock gate + - description: AXI bus clock gate + - description: AHB bus clock gate + clock-names: + items: + - const: source + - const: hclk + - const: source_cg + - const: sys_cg + - const: pclk_cg + - const: axi_cg + - const: ahb_cg + - if: + properties: + compatible: + contains: + const: mediatek,mt2712-mmc + then: + properties: + clocks: + minItems: 3 + items: + - description: source clock + - description: HCLK which used for host + - description: independent source clock gate + - description: bus clock used for internal register access (required for MSDC0/3). + clock-names: + minItems: 3 + items: + - const: source + - const: hclk + - const: source_cg + - const: bus_clk + - if: + not: + properties: + compatible: + contains: + enum: + - mediatek,mt2712-mmc + - mediatek,mt8192-mmc + then: + properties: + clocks: + minItems: 2 + items: + - description: source clock + - description: HCLK which used for host + - description: independent source clock gate + clock-names: + minItems: 2 + items: + - const: source + - const: hclk + - const: source_cg unevaluatedProperties: false