| Message ID | 20221214131117.108008-2-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] arm64: dts: mediatek: mt8195: Use P1 clocks for PCIe1 controller | expand |
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index e61944510b8e..131945c44dcc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1549,6 +1549,7 @@ u3phy1: t-phy@11e30000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x11e30000 0xe00>; + power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; status = "disabled"; u2port1: usb-phy@0 {
Assign power domain to the U3PHY1 T-PHY in otder to keep this PHY alive after unused PD shutdown and to be able to completely cut and restore power to it, for example, to save some power during system suspend/sleep. Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 + 1 file changed, 1 insertion(+)