| Message ID | 20221229101202.1655924-1-wenst@chromium.org (mailing list archive) |
|---|---|
| State | Mainlined, archived |
| Headers | show |
| Series | [v2] arm64: dts: mediatek: mt8192: Mark scp_adsp clock as broken | expand |
On Thu, Dec 29, 2022 at 06:12:02PM +0800, Chen-Yu Tsai wrote: > The scp_adsp clock controller is under the SCP_ADSP power domain. This > power domain is currently not supported nor defined. > > Mark the clock controller as broken for now, to avoid the system from > trying to access it, and causing the CPU or bus to stall. > > Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Even though personally I couldn't notice any such CPU or bus stall after manually enabling or reading back the scp_adsp_audiodsp clock without the patch applied. Thanks, Nícolas
On 29/12/2022 11:12, Chen-Yu Tsai wrote: > The scp_adsp clock controller is under the SCP_ADSP power domain. This > power domain is currently not supported nor defined. > > Mark the clock controller as broken for now, to avoid the system from > trying to access it, and causing the CPU or bus to stall. > > Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Applied thanks! > --- > Changes since v1: > - Changed "broken" to "fail" > - Rebased onto v6.2-rc1 plus v6.2-tmp/* from mediatek repo > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index dd618c563e8a..ef4fcefa2bfc 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -644,6 +644,8 @@ scp_adsp: clock-controller@10720000 { > compatible = "mediatek,mt8192-scp_adsp"; > reg = <0 0x10720000 0 0x1000>; > #clock-cells = <1>; > + /* power domain dependency not upstreamed */ > + status = "fail"; > }; > > uart0: serial@11002000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index dd618c563e8a..ef4fcefa2bfc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -644,6 +644,8 @@ scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; #clock-cells = <1>; + /* power domain dependency not upstreamed */ + status = "fail"; }; uart0: serial@11002000 {
The scp_adsp clock controller is under the SCP_ADSP power domain. This power domain is currently not supported nor defined. Mark the clock controller as broken for now, to avoid the system from trying to access it, and causing the CPU or bus to stall. Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> --- Changes since v1: - Changed "broken" to "fail" - Rebased onto v6.2-rc1 plus v6.2-tmp/* from mediatek repo arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ 1 file changed, 2 insertions(+)