From patchwork Fri Jan 13 11:06:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13100592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38696C54EBD for ; Fri, 13 Jan 2023 11:23:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1EHI3D9ujcEBj8pNTKYwfUSa0VZoyEQKxHNkE/MdUV0=; b=AEaqD4wV0graA7WPU7LNEj758f IU1TKgVKE0+jNN1ilLAyj+K7w3gaf+jW00Ouq1fRXE1gFE424AGpmJ5Ssnl+AoW/A2e3UCUtJGrrr kxQ518hJGxLgu2h6cSJPCZCkX/KHYfcriT7EuQ2SVj6zSP6WNn7stiVfNEWJUHL4qsaS03RLEB8Ff 53IAyui/PLC5liiucaIEKiKwfikQxPvYKz/z7UhjHzgyozxLf9Qh2WKYKSmPJYpMYe64+Tu9pIWqp 7d8MzKlnsQ+mXscI1rU0cH6Us1hW7Sfv6VN0w5WICcrD0f/j+SwQ+b4MGjdlKVnXMbfUCI7RPiwJY Q9BHIi3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGI9Q-0028Az-MI; Fri, 13 Jan 2023 11:23:12 +0000 Received: from madras.collabora.co.uk ([46.235.227.172]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pGHtz-0020cL-6D; Fri, 13 Jan 2023 11:07:17 +0000 Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 643EE6602DD6; Fri, 13 Jan 2023 11:07:12 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673608033; bh=NchnhQJ8/NsCOmF+ugDdtTzoMIg4fvva0j2fRFAtkyM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ayPI0A1NXgS0JGq5bnthfTXePHiqwhWv/G+WjqnV3+p5Ml53IfvBRkM097/qlRqMp yfDnCTFYN3698+XUTlUcQla7H/Mdg5QM8OKqNkwGGz9fbFN8HQfAzGa/ZqLWXHr9jm gdZqZDDjbQ7tmBV7qqZZJecceO9hWL5TOItLMVRmKcUtJpAQ4Cev3an1OVc6TED4L7 z8ZNCN5AJcuLR/fD0s2edXguShye2Hcdw9saUlxJpArD9IKHjpu0nXRJR6efRbkbdg k+sEWkBdzk5UNmXASj3kcFOK0RrEYj7FpG4v64nc+uuQ/aRUMr/AjOUK1svxxGwQHR Q+pkEnQgJ3w6w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v3 09/23] clk: mediatek: mt8173: Remove mtk_clk_enable_critical() Date: Fri, 13 Jan 2023 12:06:02 +0100 Message-Id: <20230113110616.111001-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113110616.111001-1-angelogioacchino.delregno@collabora.com> References: <20230113110616.111001-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230113_030715_702006_C4782A6C X-CRM114-Status: GOOD ( 13.28 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The entire point of mtk_clk_enable_critical() is to raise the refcount of some clocks so that they won't be turned off during runtime, but this is the same as what the CLK_IS_CRITICAL flag does. Set CLK_IS_CRITICAL on all of the critical clocks and remove the aforementioned function as a cleanup. No functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8173.c | 41 ++++++++++++------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 0163d27e8795..787ab87036a0 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -546,8 +546,11 @@ static const struct mtk_composite cpu_muxes[] = { static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), - MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23), + MUX_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", + ddrphycfg_parents, 0x0040, 16, 1, 23, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31), /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), @@ -581,7 +584,9 @@ static const struct mtk_composite top_muxes[] = { */ MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0), MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15), - MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23), + MUX_GATE_FLAGS(CLK_TOP_CCI400_SEL, "cci400_sel", + cci400_parents, 0x00a0, 16, 3, 23, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31), /* CLK_CFG_7 */ MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7), @@ -596,7 +601,8 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7), MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15), MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23), - MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2), + MUX_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24), DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0), @@ -846,23 +852,8 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = { } }; -static struct clk_hw_onecell_data *mt8173_top_clk_data; -static struct clk_hw_onecell_data *mt8173_pll_clk_data; static struct clk_hw_onecell_data *infra_clk_data; -static void mtk_clk_enable_critical(void) -{ - if (!mt8173_top_clk_data || !mt8173_pll_clk_data) - return; - - clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA15PLL]->clk); - clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA7PLL]->clk); - clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_MEM_SEL]->clk); - clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk); - clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_CCI400_SEL]->clk); - clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk); -} - static int clk_mt8173_topck_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; @@ -874,7 +865,7 @@ static int clk_mt8173_topck_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); if (IS_ERR_OR_NULL(clk_data)) return -ENOMEM; @@ -896,7 +887,6 @@ static int clk_mt8173_topck_probe(struct platform_device *pdev) if (r) goto unregister_composites; - mtk_clk_enable_critical(); return 0; unregister_composites: @@ -1051,8 +1041,10 @@ static const struct mtk_pll_div_table mmpll_div_table[] = { }; static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, 0, 21, 0x204, 24, 0x0, 0x204, 0), - PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, 0, 21, 0x214, 24, 0x0, 0x214, 0), + PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO, + 21, 0x204, 24, 0x0, 0x204, 0), + PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO, + 21, 0x214, 24, 0x0, 0x214, 0), PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0), PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14), PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table), @@ -1079,7 +1071,7 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev) if (!base) return PTR_ERR(base); - mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (IS_ERR_OR_NULL(clk_data)) return -ENOMEM; @@ -1104,7 +1096,6 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev) if (r) goto unregister_ref2usb; - mtk_clk_enable_critical(); return 0; unregister_ref2usb: