From patchwork Thu Jan 26 08:53:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13116808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D45B2C54E94 for ; Thu, 26 Jan 2023 09:00:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=MqmGbvtohrr9AwXpIavOukLiaH9UsuX6IGvABUv/8JA=; b=DsiH9I0u6GumP7am3Z7kxXAVKA McJji3ikGxOylsYoxxZLCLHhHxn4sMb8FrmxkSi0YpbeT+W4jspAnjO1apJIcxMn3rDFi5MQmFZSi fEsQv8j64oy6oJBTKuI4xsApjhaYLjv8tuVUol7W2i4vfKp/hU/7Q5Ry0yn30ulEcxZ3zcFWdRgJ3 9PKkDVRJmZl/JSYd46LgvMuWSiLsh/N6AkK2VoeTZ4JQFihvLrzZZCxy2ih4DUDOdLuSHoWdwHuko maT85/uYAf74K2aCC+tjQdw0UeCQrXl41IlsWODERKeqvs6Vn+bEY6DszIU1upVX3pyq8jYqPNhWy drwPCn+g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKy71-00AB0X-Tv; Thu, 26 Jan 2023 09:00:03 +0000 Received: from madras.collabora.co.uk ([46.235.227.172]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKy0j-00A8JU-1F; Thu, 26 Jan 2023 08:53:35 +0000 Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E46286602E78; Thu, 26 Jan 2023 08:53:30 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674723211; bh=oWl0cctAa7ZwmyC5Ywb+4z1cuC9Q0pBS1rdEG+qBoHM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tv34dzq8/zvQ56rn+b98dM0W2HBHbbfENlA/yBM/c27HTXvKFKJROC1HKERVK8OAY 2ugvW8zPmlxB5KM9iOJXjetrnUPpP+ZDIWWHDByOl3owirn4X8KooRmOAyKS5XVWzp R2zrW5lDFe/7ay/o48jV6qUe+RhzApriqZR9EsNs+FHEKr/p+FTL1kNvMqMfzY8Cni RHyN3VzmxjNpCYXhKXVVahrppctr5XcHrS7IAPryA0HDz0hrhFEisRQa1gOU2AMb0x iLYKIU/hEyi5jvdzWdosdJJFGFywu7vpeXgHTz72lqRDf/oDgiheNhbLgxbeeo2+4O 8QHdRvQ1Usyng== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 5/6] clk: mediatek: mt8192: Add support for frequency hopping through FHCTL Date: Thu, 26 Jan 2023 09:53:20 +0100 Message-Id: <20230126085321.87267-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> References: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230126_005333_386416_1C9A3446 X-CRM114-Status: GOOD ( 13.98 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192.c | 67 ++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 61299960d28a..0f9f10172148 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -12,10 +12,12 @@ #include #include +#include "clk-fhctl.h" #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" #include "clk-pll.h" +#include "clk-pllfh.h" #include #include @@ -1042,6 +1044,57 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), }; +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL0, + FH_ARMPLL_BL1, + FH_ARMPLL_BL2, + FH_ARMPLL_BL3, + FH_CCIPLL, + FH_MFGPLL, + FH_MEMPLL, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_ADSPPLL, + FH_APUPLL, + FH_TVDPLL, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data = { \ + .pll_id = _pllid, \ + .fh_id = _fhid, \ + .fh_ver = FHCTL_PLLFH_V2, \ + .fhx_offset = _offset, \ + .dds_mask = GENMASK(21, 0), \ + .slope0_value = 0x6003c97, \ + .slope1_value = 0x6003c97, \ + .sfstrx_en = BIT(2), \ + .frddsx_en = BIT(1), \ + .fhctlx_en = BIT(0), \ + .tgl_org = BIT(31), \ + .dvfs_tri = BIT(31), \ + .pcwchg = BIT(31), \ + .dt_val = 0x0, \ + .df_val = 0x9, \ + .updnlmt_shft = 16, \ + .msk_frddsx_dys = GENMASK(23, 20), \ + .msk_frddsx_dts = GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] = { + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154), +}; + /* Register mux notifier for MFG mux */ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) { @@ -1068,17 +1121,24 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; + const u8 *fhctl_node = "mediatek,mt8192-fhctl"; int r; clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); + if (r) + goto free_clk_data; + r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); if (r) - goto free_clk_data; + goto unregister_plls; r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -1088,6 +1148,9 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev) unregister_gates: mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); +unregister_plls: + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return r;