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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id hu21-20020a05600ca29500b003eaee9e0d22sm12986242wmb.33.2023.03.07.05.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:18:17 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 14:17:45 +0100 Subject: [PATCH v2 16/18] arm64: dts: mediatek: add cpufreq support for mt8365-evk MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v2-16-6ec7cdb10ccf@baylibre.com> References: <20230203-evk-board-support-v2-0-6ec7cdb10ccf@baylibre.com> In-Reply-To: <20230203-evk-board-support-v2-0-6ec7cdb10ccf@baylibre.com> To: =?unknown-8bit?q?Zhiyong_Tao_=3Czhiyong=2Etao=40mediatek=2Ecom=3E=2C_Gue?= =?unknown-8bit?q?nter_Roeck_=3Clinux=40roeck-us=2Enet=3E=2C_Linus_Walleij_?= =?unknown-8bit?q?=3Clinus=2Ewalleij=40linaro=2Eorg=3E=2C?= =?unknown-8bit?q?_Bernhard_Rosenkr=C3=A4nzer_=3Cbero=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?AngeloGioacchino_Del_Regno_=3Cangelogioacchino=2Edelregno?= =?unknown-8bit?q?=40collabora=2Ecom=3E=2C?= =?unknown-8bit?q?_Ulf_Hansson_=3Culf=2Ehansson=40linaro=2Eorg=3E=2C_Wim_Van_?= =?unknown-8bit?q?Sebroeck_=3Cwim=40linux-watchdog=2Eorg=3E=2C?= =?unknown-8bit?q?_Krzysztof_Kozlowski_=3Ckrzysztof=2Ekozlowski+dt=40linaro?= =?unknown-8bit?q?=2Eorg=3E=2C_Chaotian_Jing_=3Cchaotian=2Ejing=40mediatek?= =?unknown-8bit?q?=2Ecom=3E=2C?= =?unknown-8bit?q?_Rob_Herring_=3Crobh+dt=40kernel=2Eorg=3E=2C_Wenbin_Mei_=3C?= =?unknown-8bit?q?wenbin=2Emei=40mediatek=2Ecom=3E=2C_Matthias_Brugger_=3Cma?= =?unknown-8bit?q?tthias=2Ebgg=40gmail=2Ecom=3E?= Cc: linux-mmc@vger.kernel.org, Alexandre Bailon , devicetree@vger.kernel.org, Amjad Ouled-Ameur , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, Alexandre Mergnat , linux-mediatek@lists.infradead.org, Fabien Parent X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1073; i=amergnat@baylibre.com; h=from:subject:message-id; bh=Y4L/p189NH3SAVW+4HN4eciI82eYHFCxYrkIH+HpMQA=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkBzmF7wCSDr+Hb9Hj41DRSfR+NA3e5/YZy+L+V2X5 cbhN3EWJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAc5hQAKCRArRkmdfjHURddmEA CZP7USN8+ewJ5/hPAB71aQM/MDCXizoneBZIDTyyayggRrWtd8o3jQPANBQ+JdrbYfVGKS0QLqiSsG CAwBNbeJlb129nPQdm+9rYTYZRAIiqeBWRWhV1TIxdHX4g9Nf1tTmCrPSXvk7uWsL6un2cJLeuz8dQ oNzJVyoQi83jsat63vHwma+CBDKkAi4I+QY3PBlWyNZMrd063jYMLts9QFEN79vsMmPv2wgYYi3B/M wNTZIu7jyhYatJXDS5mcSilqOUyaskIelA5xYkvt8iQGxHYIesLuHCCsBc2U9OJcgm1Q1eu5JXTIj3 NWZGWJSbe0VMyVMoEjeVVCzsKjXw9F6AeY7HFf4/00wE+7lK0OnzEUBbR6ONC2hGHT/4bSM36wfXG9 ftX3Y+oWCF3SJkImT5/EGIR5tk8PbNzqkrNVkOC90uJHdfIiNLtBfykYsJBRRDcz8JQpEhywG4Ghk8 3bhwkAp+WKgZtDdRi5VyuGY2ogHE2GZPl9jj31DLwHibcqAjrEVF5BC7/R+GRBRGVKpT8VsXh5eL9y 4FJbb626i8rCPmnERbuLk8skagHEfw5h83SEINMmpdl4sshX/eY0GvO1dJVagF2/zR+bi/tmdT2LdS TsH87WbhngZIfaqP8bFgT5g4+fsZa8S63bGHVGTEU8RJBRJ+K8GRz9q5A8EQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230307_051818_480047_BF315B8A X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org In order to have cpufreq support, this patch adds proc-supply and sram-supply for each CPU. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 1820daad6da3..edf3a4b6a76e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -88,6 +88,26 @@ optee_reserved: optee@43200000 { }; }; +&cpu0 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu1 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu2 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu3 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + ðernet { pinctrl-names = "default"; pinctrl-0 = <ðernet_pins>;