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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id hu21-20020a05600ca29500b003eaee9e0d22sm12986242wmb.33.2023.03.07.05.18.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:18:08 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 14:17:38 +0100 Subject: [PATCH v2 09/18] arm64: dts: mediatek: add mmc support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v2-9-6ec7cdb10ccf@baylibre.com> References: <20230203-evk-board-support-v2-0-6ec7cdb10ccf@baylibre.com> In-Reply-To: <20230203-evk-board-support-v2-0-6ec7cdb10ccf@baylibre.com> To: =?unknown-8bit?q?Zhiyong_Tao_=3Czhiyong=2Etao=40mediatek=2Ecom=3E=2C_Gue?= =?unknown-8bit?q?nter_Roeck_=3Clinux=40roeck-us=2Enet=3E=2C_Linus_Walleij_?= =?unknown-8bit?q?=3Clinus=2Ewalleij=40linaro=2Eorg=3E=2C?= =?unknown-8bit?q?_Bernhard_Rosenkr=C3=A4nzer_=3Cbero=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?AngeloGioacchino_Del_Regno_=3Cangelogioacchino=2Edelregno?= =?unknown-8bit?q?=40collabora=2Ecom=3E=2C?= =?unknown-8bit?q?_Ulf_Hansson_=3Culf=2Ehansson=40linaro=2Eorg=3E=2C_Wim_Van_?= =?unknown-8bit?q?Sebroeck_=3Cwim=40linux-watchdog=2Eorg=3E=2C?= =?unknown-8bit?q?_Krzysztof_Kozlowski_=3Ckrzysztof=2Ekozlowski+dt=40linaro?= =?unknown-8bit?q?=2Eorg=3E=2C_Chaotian_Jing_=3Cchaotian=2Ejing=40mediatek?= =?unknown-8bit?q?=2Ecom=3E=2C?= =?unknown-8bit?q?_Rob_Herring_=3Crobh+dt=40kernel=2Eorg=3E=2C_Wenbin_Mei_=3C?= =?unknown-8bit?q?wenbin=2Emei=40mediatek=2Ecom=3E=2C_Matthias_Brugger_=3Cma?= =?unknown-8bit?q?tthias=2Ebgg=40gmail=2Ecom=3E?= Cc: linux-mmc@vger.kernel.org, Alexandre Bailon , devicetree@vger.kernel.org, Amjad Ouled-Ameur , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, Alexandre Mergnat , linux-mediatek@lists.infradead.org, Fabien Parent X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2130; i=amergnat@baylibre.com; h=from:subject:message-id; bh=b/w2WNUqtK9XOnggUHaJqIMMUWpiozZDP8P43Z1auyg=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkBzmFy4JhC6orCMChEoIwF/YLwuuJqJQzpRXkhWyY 8KWIwOeJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAc5hQAKCRArRkmdfjHURa5JEA C6Xlkjc++w6xtOTyvSysrEiqtVxFkMzX8XyhxnRjDzvfzR85SAIfqY9spKK4vrnAHt1JjW2wpYbLEL OP7gZY7I/c/X2BFe1R58H8HL203BSXbsDKGoQamz28W309Jwkj3RBQ0O/LcCwyREPlHrGVsaj6uTx3 nlgo4lYxsotV97/fJ+BTU6Tu5KqTSlkH0Vc5TML4jFw3cXbKuc/zMF8uJXBwvothDSuH+td/jLZhxS wgbcapn1rXK+2aNZCgQBLvsJJUTHNXMLIk4NWGBYS2wUrHIPM9/NN5wtkRrye11TOOMy4Ti0zDO5KM HRwXLBGe41fWjja4j3SVNQFjFDFLEpuRPWL4Ajnzqd+114WK6L1P51v24so9hXMfbyZW9F9gKGs1sX Pjnhgf1Elv3BFwJU68QM+tUR92hAMhGoYbUtvQbt/cRLDZ956Br5Hv7yLPDo/MME59wQ8tk1xEZCF6 x23qQtOfnu7aQSo14T5lpcd9fXq9xGG4s3d20u0MzBWEst/FL5HI80O4199JRrouP3GtQ5YTZbzn8d 55ntQ3Ab1e0DOU4wwsj/VfbKx2ekL3Al66bJNt2WUexSs5hq27UtvUi3Rc6Ta8VXAqYtlW7NTIx7GG j5EAqLaEheFtO9mI2IxyzAQFvyhimx2UftqunWyqcqGZCxZtX7lUBdbbyNAQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230307_131811_486154_205BE378 X-CRM114-Status: UNSURE ( 9.86 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org There are three ports of MSDC (MMC and SD Controller), which are: - MSDC0: EMMC5.1 - MSDC1: SD3.0/SDIO3.0 - MSDC2: SDIO3.0+ Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 687011353f69..a67eeca28da5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -399,6 +399,45 @@ usb_host: usb@11200000 { }; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&infracfg CLK_IFR_MSDC0_HCLK>, + <&infracfg CLK_IFR_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&infracfg CLK_IFR_MSDC1_HCLK>, + <&infracfg CLK_IFR_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11250000 0 0x1000>, + <0 0x11c60000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, + <&infracfg CLK_IFR_MSDC2_HCLK>, + <&infracfg CLK_IFR_MSDC2_SRC>, + <&infracfg CLK_IFR_MSDC2_BK>, + <&infracfg CLK_IFR_AP_MSDC0>; + clock-names = "source", "hclk", "source_cg", + "bus_clk", "sys_cg"; + status = "disabled"; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>;