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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id 1-20020a05600c22c100b003eeb1d6a470sm3370171wmg.13.2023.03.31.10.55.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 10:55:43 -0700 (PDT) From: Alexandre Mergnat Date: Fri, 31 Mar 2023 19:54:53 +0200 Subject: [PATCH v4 09/11] arm64: dts: mediatek: add OPP support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v4-9-5cffe66a38c0@baylibre.com> References: <20230203-evk-board-support-v4-0-5cffe66a38c0@baylibre.com> In-Reply-To: <20230203-evk-board-support-v4-0-5cffe66a38c0@baylibre.com> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Chaotian Jing , Ulf Hansson , Wenbin Mei , Linus Walleij , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nz?= =?utf-8?q?er?= Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, Alexandre Bailon , Fabien Parent , Amjad Ouled-Ameur , Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3661; i=amergnat@baylibre.com; h=from:subject:message-id; bh=vbee9YlPZnb6kFNtpMf6YbhiqwJ/puB0VHW9S9J3p/Y=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkJx6U8qi3/eBgn1928vnMIxSgut2P2oseEaXCwFbv 67PPr/mJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZCcelAAKCRArRkmdfjHURej4D/ 91YCFkicGT0TlcSGqT0D6mA0aMFzYIkzkyY1fyPYfZIOzvqyrGcgwZp8096BD/32FBBawocK13NnPN Ka3FluzrS3GlYCPzolybM+5v3Od2KVXINBsouVBSPjorglDVBB8RrxbeKEyMLgiyYQKFWU5Ux0ZWNQ bKXiC6nL53OVgPrykwIlOrfWU2Qq7UluH24Uvpi8Ph2J+MrLNRpvOGEPPwVbUocBuFX0MacskXXOt4 FaLFGc2WnQ6vwBFrcurQGJMLiqpfmQzRt0x71P97dhaHmlD33fx9za371N9CsTK9xxwC4P/TI3H+Xr JH0ntiKc1lIduYtj65JPuuzSb8FI9nQ9GfWWJTFQeYwpeAS5bXdDxe2sE4xXj2FfVIjbS1BJktWKNP zEjxDgwmFPtk4xM/bPo+Uy+a7jeAyu7qAgjPI9fFhJCn6NBgGBorJbrTCjt9zfgftaCpL0wcID9lcy BsNxhIbmjOuGSiejjTYC7ezUd9ukXoQR9PBBfj5QQPAIKWmuAw+7BgZ8K5lyHR1jr00jBxfwL10myh 0HH0NFWE58zFpKB+uYm6khCcuLN2pgFmzltrXR/EG4uJRpvllWtCgpSf0Ds2wsviwW4GXUVQ1WsQh4 Qrxf9361pryPzLgTNTJu4lKq6OBFitwz0bei0OPqLlIsGxChTgLmH1zuoUFQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230331_105544_693605_F4BA1C8A X-CRM114-Status: GOOD ( 10.12 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org In order to have cpufreq support, this patch adds generic Operating Performance Points support. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 101 +++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index bb45aab2e6a9..cfe0c67ad61f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -20,6 +20,91 @@ cpus { #address-cells = <1>; #size-cells = <0>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <650000>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <668750>; + }; + + opp-987000000 { + opp-hz = /bits/ 64 <987000000>; + opp-microvolt = <687500>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <706250>; + }; + + opp-1125000000 { + opp-hz = /bits/ 64 <1125000000>; + opp-microvolt = <725000>; + }; + + opp-1216000000 { + opp-hz = /bits/ 64 <1216000000>; + opp-microvolt = <750000>; + }; + + opp-1308000000 { + opp-hz = /bits/ 64 <1308000000>; + opp-microvolt = <775000>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <800000>; + }; + + opp-1466000000 { + opp-hz = /bits/ 64 <1466000000>; + opp-microvolt = <825000>; + }; + + opp-1533000000 { + opp-hz = /bits/ 64 <1533000000>; + opp-microvolt = <850000>; + }; + + opp-1633000000 { + opp-hz = /bits/ 64 <1633000000>; + opp-microvolt = <887500>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <912500>; + }; + + opp-1767000000 { + opp-hz = /bits/ 64 <1767000000>; + opp-microvolt = <937500>; + }; + + opp-1834000000 { + opp-hz = /bits/ 64 <1834000000>; + opp-microvolt = <962500>; + }; + + opp-1917000000 { + opp-hz = /bits/ 64 <1917000000>; + opp-microvolt = <993750>; + }; + + opp-2001000000 { + opp-hz = /bits/ 64 <2001000000>; + opp-microvolt = <1025000>; + }; + }; + cpu-map { cluster0 { core0 { @@ -50,6 +135,10 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -65,6 +154,10 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -80,6 +173,10 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -95,6 +192,10 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; l2: l2-cache {