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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id t4-20020a5d6a44000000b002e558f1c45fsm4471446wrw.69.2023.04.07.05.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 05:59:51 -0700 (PDT) From: Alexandre Mergnat Date: Fri, 07 Apr 2023 14:59:28 +0200 Subject: [PATCH v5 09/12] arm64: dts: mediatek: add ethernet support for mt8365-evk MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v5-9-1883c1b405ad@baylibre.com> References: <20230203-evk-board-support-v5-0-1883c1b405ad@baylibre.com> In-Reply-To: <20230203-evk-board-support-v5-0-1883c1b405ad@baylibre.com> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Chaotian Jing , Ulf Hansson , Wenbin Mei , Linus Walleij , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nz?= =?utf-8?q?er?= Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, Alexandre Bailon , Fabien Parent , Amjad Ouled-Ameur , Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2431; i=amergnat@baylibre.com; h=from:subject:message-id; bh=qis7u9dUHrWOnbhiX3GDPhugjgVXBkDPDVj5m9M4200=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkMBO6jGoMhPSC8/u2mSdWUkp0vvyJ26Nfy26JOIW8 7jrUXZOJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZDATugAKCRArRkmdfjHURckkD/ 4gFyqdOtBUpSZL/GjaJpSHnrJbsKxp5S2gg3Ij8KzH/+4zmxfuW00BnrrFqeKxrmzHhXO3yEWeNKFA 8uJKCPQyNmRC+wKcr0tHSLsh5t+Ml7eDvJI0gSk/6RiXeM0+s0QG6n7U+tJ1+oHa6LZ6Jrc80XuUQv R8idXfjbx2V4qTu2G2FZnX0uyvzSJa84DHASgEH367zU47WRvPj5PTygyJkJnGHU8Adw+8aFdGcOx8 jmASRrjwy98hILGvvfe4K3mNwSFzxuRzuqKgwBTQmA3Wd9v1zspW5FZhmOenzdOyciCtrKx9f6e0yT sr3cKu8zetW1EkekQ9F1cQO7+rIucwRo6rmAHfeenxRfYG4ZUp3qAP3LLG7LpJHJmfN46l8gtq1ybA bvAiL81lfKwC6Bb9Yu+GRrzCLpVZEJ9bZeA7mSlbC1MnE6vwiBKgjqKGzszEI1n7mLiRsfjdmL8sqs fE/54ecjpCCQucF4umTyW74hT/Q7idxLC6E+KtV8IkJ9GaIQpnldkmYsxTpnESEqvBcW5JohL6kQZP hCIBbtHPxZ1lN/Ksvpnrqg20USMvnASYdChrtZTnjsp+l8By4JXaDZsarpni//esIdHPAt7sC37Fwl I/tPV8tZ8E9YVW/Al8eTb16sfYi0ktIKOEdIKbZSF9gko4Us8M8Zz6/eMI3A== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230407_055953_747271_B381F40A X-CRM114-Status: GOOD ( 11.88 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org - Enable "vibr" and "vsim2" regulators to power the ethernet chip. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 57 +++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 9760f181eb34..431078f8670e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -88,6 +88,28 @@ optee_reserved: optee@43200000 { }; }; +ðernet { + pinctrl-0 = <ðernet_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + /* + * Ethernet and HDMI (DSI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + */ + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &i2c0 { clock-frequency = <100000>; pinctrl-0 = <&i2c0_pins>; @@ -137,12 +159,47 @@ &mt6357_pmic { #interrupt-cells = <2>; }; +/* Needed by analog switch (multiplexer), HDMI and ethernet */ +&mt6357_vibr_reg { + regulator-always-on; +}; + /* Needed by MSDC1 */ &mt6357_vmc_reg { regulator-always-on; }; +/* Needed by ethernet */ +&mt6357_vsim2_reg { + regulator-always-on; +}; + &pio { + ethernet_pins: ethernet-pins { + phy_reset_pins { + pinmux = ; + }; + + rmii_pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + gpio_keys: gpio-keys-pins { pins { pinmux = ;