diff mbox series

[v1,13/45] clk: mediatek: mt8167: Compress GATE_TOPx macros

Message ID 20230206152928.918562-14-angelogioacchino.delregno@collabora.com (mailing list archive)
State New
Headers show
Series MediaTek clocks: full module build and cleanups | expand

Commit Message

AngeloGioacchino Del Regno Feb. 6, 2023, 3:28 p.m. UTC 
Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros.
No functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8167.c | 88 +++++++++----------------------
 1 file changed, 24 insertions(+), 64 deletions(-)

Comments

Chen-Yu Tsai Feb. 7, 2023, 7:30 a.m. UTC | #1 
On Mon, Feb 6, 2023 at 11:30 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros.
> No functional changes.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/clk/mediatek/clk-mt8167.c | 88 +++++++++----------------------
>  1 file changed, 24 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c
> index 91669ebafaf9..97a443fdfc77 100644
> --- a/drivers/clk/mediatek/clk-mt8167.c
> +++ b/drivers/clk/mediatek/clk-mt8167.c
> @@ -736,77 +736,37 @@ static const struct mtk_gate_regs top5_cg_regs = {
>         .sta_ofs = 0x44,
>  };
>
> -#define GATE_TOP0(_id, _name, _parent, _shift) {       \
> -               .id = _id,                              \
> -               .name = _name,                          \
> -               .parent_name = _parent,                 \
> -               .regs = &top0_cg_regs,                  \
> -               .shift = _shift,                        \
> -               .ops = &mtk_clk_gate_ops_setclr,        \
> -       }
> +#define GATE_TOP0(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &top0_cg_regs,            \
> +                _shift, &mtk_clk_gate_ops_setclr)

Nit: 100 characters should be enough to fit the whole GATE_MTK part in one
line.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
AngeloGioacchino Del Regno Feb. 7, 2023, 9:17 a.m. UTC | #2 
Il 07/02/23 08:30, Chen-Yu Tsai ha scritto:
> On Mon, Feb 6, 2023 at 11:30 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros.
>> No functional changes.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   drivers/clk/mediatek/clk-mt8167.c | 88 +++++++++----------------------
>>   1 file changed, 24 insertions(+), 64 deletions(-)
>>
>> diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c
>> index 91669ebafaf9..97a443fdfc77 100644
>> --- a/drivers/clk/mediatek/clk-mt8167.c
>> +++ b/drivers/clk/mediatek/clk-mt8167.c
>> @@ -736,77 +736,37 @@ static const struct mtk_gate_regs top5_cg_regs = {
>>          .sta_ofs = 0x44,
>>   };
>>
>> -#define GATE_TOP0(_id, _name, _parent, _shift) {       \
>> -               .id = _id,                              \
>> -               .name = _name,                          \
>> -               .parent_name = _parent,                 \
>> -               .regs = &top0_cg_regs,                  \
>> -               .shift = _shift,                        \
>> -               .ops = &mtk_clk_gate_ops_setclr,        \
>> -       }
>> +#define GATE_TOP0(_id, _name, _parent, _shift)                 \
>> +       GATE_MTK(_id, _name, _parent, &top0_cg_regs,            \
>> +                _shift, &mtk_clk_gate_ops_setclr)
> 
> Nit: 100 characters should be enough to fit the whole GATE_MTK part in one
> line.
> 

Wanted to stay below 90, but there's effectively no real reason to do that,
so let's go to 100 cols!

> Otherwise,
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>


Cheers,
Angelo
diff mbox series

Patch

diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c
index 91669ebafaf9..97a443fdfc77 100644
--- a/drivers/clk/mediatek/clk-mt8167.c
+++ b/drivers/clk/mediatek/clk-mt8167.c
@@ -736,77 +736,37 @@  static const struct mtk_gate_regs top5_cg_regs = {
 	.sta_ofs = 0x44,
 };
 
-#define GATE_TOP0(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top0_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr,	\
-	}
+#define GATE_TOP0(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top0_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr)
 
-#define GATE_TOP0_I(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top0_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-	}
+#define GATE_TOP0_I(_id, _name, _parent, _shift)		\
+	GATE_MTK(_id, _name, _parent, &top0_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr_inv)
 
-#define GATE_TOP1(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top1_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr,	\
-	}
+#define GATE_TOP1(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top1_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr)
 
-#define GATE_TOP2(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top2_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr,	\
-	}
+#define GATE_TOP2(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top2_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr)
 
-#define GATE_TOP2_I(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top2_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-	}
+#define GATE_TOP2_I(_id, _name, _parent, _shift)		\
+	GATE_MTK(_id, _name, _parent, &top2_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr_inv)
 
-#define GATE_TOP3(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top3_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr,	\
-	}
+#define GATE_TOP3(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top3_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr)
 
-#define GATE_TOP4_I(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top4_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-	}
+#define GATE_TOP4_I(_id, _name, _parent, _shift)		\
+	GATE_MTK(_id, _name, _parent, &top4_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr_inv)
 
-#define GATE_TOP5(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top5_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr,	\
-	}
+#define GATE_TOP5(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top5_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_no_setclr)
 
 static const struct mtk_gate top_clks[] __initconst = {
 	/* TOP0 */