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Thu, 21 Sep 2023 07:32:57 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id lt12-20020a170906fa8c00b009a219ecbaf1sm1153327ejb.85.2023.09.21.07.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 07:32:56 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 21 Sep 2023 16:32:45 +0200 Subject: [PATCH v5 6/7] arm64: dts: mediatek: add larb support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230207-iommu-support-v5-6-fa6f03680832@baylibre.com> References: <20230207-iommu-support-v5-0-fa6f03680832@baylibre.com> In-Reply-To: <20230207-iommu-support-v5-0-fa6f03680832@baylibre.com> To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Krzysztof Kozlowski , Conor Dooley Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_153259_447638_A90317F3 X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Local arbiter (LARB) is a component of Smart Multimedia Interface (SMI), used to help the memory management (IOMMU). This patch add 4 LARBs and 2 clocks for the larb1 and larb3 support. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 59 ++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index a03b8c0da68b..afcfa1dd242e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -735,12 +735,71 @@ smi_common: smi@14002000 { power-domains = <&spm MT8365_POWER_DOMAIN_MM>; }; + larb0: larb@14003000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + mediatek,larb-id = <0>; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + larb2: larb@15001000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_IMG>, + <&camsys CLK_CAM_LARB2>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + mediatek,larb-id = <2>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8365-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb3: larb@16010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; + mediatek,larb-id = <3>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8365-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb@17010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; + mediatek,larb-id = <1>; + }; + apu: syscon@19020000 { compatible = "mediatek,mt8365-apu", "syscon"; reg = <0 0x19020000 0 0x1000>;