| Message ID | 20230223134345.82625-17-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable GPU with DVFS support on MediaTek SoCs | expand |
On Thu, Feb 23, 2023 at 9:44 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > Add a GPU node for MT8186 SoC but keep it disabled. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index a0d3e1f731bd..dc760e4dafdf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1075,6 +1075,23 @@ mfgsys: clock-controller@13000000 { #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "mediatek,mt8186-mali", "mediatek,mt8183b-mali", + "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + + clocks = <&mfgsys CLK_MFG_BG3D>; + interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "job", "mmu", "gpu"; + power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, + <&spm MT8186_POWER_DOMAIN_MFG3>; + power-domain-names = "core0", "core1"; + #cooling-cells = <2>; + status = "disabled"; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8186-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>;
Add a GPU node for MT8186 SoC but keep it disabled. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)