diff mbox series

[2/2] clk: mediatek: mt8365: remove the max clock number defines

Message ID 20230517-fix-clk-index-v1-2-142077a1732b@baylibre.com (mailing list archive)
State New, archived
Headers show
Series Fix and clean MT8365 clock indexes | expand

Commit Message

Alexandre Mergnat May 17, 2023, 8:28 a.m. UTC 
Since we swap to the generic MTK probe function [1], the *_NR_CLK
defines used to know the number of defined clocks are no longer
necessary. This patch remove all *_NR_CLK.

[1]: Commit ffe91cb28f6a ("clk: mediatek: mt8365: Convert to
     mtk_clk_simple_{probe,remove}()")

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
 include/dt-bindings/clock/mediatek,mt8365-clk.h | 18 ------------------
 1 file changed, 18 deletions(-)

Comments

Krzysztof Kozlowski May 17, 2023, 8:41 a.m. UTC | #1 
On 17/05/2023 10:28, Alexandre Mergnat wrote:
> Since we swap to the generic MTK probe function [1], the *_NR_CLK
> defines used to know the number of defined clocks are no longer
> necessary. This patch remove all *_NR_CLK.

Please do not use "This commit/patch", but imperative mood. See longer
explanation here:
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95

> 
> [1]: Commit ffe91cb28f6a ("clk: mediatek: mt8365: Convert to
>      mtk_clk_simple_{probe,remove}()")
> 
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>


Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.

And what about other users of bindings?

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/mediatek,mt8365-clk.h b/include/dt-bindings/clock/mediatek,mt8365-clk.h
index fd59c8bdeb24..a1df91f73d73 100644
--- a/include/dt-bindings/clock/mediatek,mt8365-clk.h
+++ b/include/dt-bindings/clock/mediatek,mt8365-clk.h
@@ -142,7 +142,6 @@ 
 #define CLK_TOP_CONN_26M		132
 #define CLK_TOP_DSP_32K			133
 #define CLK_TOP_DSP_26M			134
-#define CLK_TOP_NR_CLK			135
 
 /* INFRACFG */
 #define CLK_IFR_PMIC_TMR		0
@@ -214,11 +213,9 @@ 
 #define CLK_IFR_SSUSB_SYS		66
 #define CLK_IFR_SSUSB_REF		67
 #define CLK_IFR_SSUSB_XHCI		68
-#define CLK_IFR_NR_CLK			69
 
 /* PERICFG */
 #define CLK_PERIAXI			0
-#define CLK_PERI_NR_CLK			1
 
 /* APMIXEDSYS */
 #define CLK_APMIXED_ARMPLL		0
@@ -238,7 +235,6 @@ 
 
 /* GCE */
 #define CLK_GCE_FAXI			0
-#define CLK_GCE_NR_CLK			1
 
 /* AUDIOTOP */
 #define CLK_AUD_AFE			0
@@ -259,40 +255,31 @@ 
 #define CLK_AUD_I2S2_BK			15
 #define CLK_AUD_I2S3_BK			16
 #define CLK_AUD_I2S4_BK			17
-#define CLK_AUD_NR_CLK			18
 
 /* MIPI_CSI0A */
 #define CLK_MIPI0A_CSR_CSI_EN_0A	0
-#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK	1
 
 /* MIPI_CSI0B */
 #define CLK_MIPI0B_CSR_CSI_EN_0B	0
-#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK	1
 
 /* MIPI_CSI1A */
 #define CLK_MIPI1A_CSR_CSI_EN_1A	0
-#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK	1
 
 /* MIPI_CSI1B */
 #define CLK_MIPI1B_CSR_CSI_EN_1B	0
-#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK	1
 
 /* MIPI_CSI2A */
 #define CLK_MIPI2A_CSR_CSI_EN_2A	0
-#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK	1
 
 /* MIPI_CSI2B */
 #define CLK_MIPI2B_CSR_CSI_EN_2B	0
-#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK	1
 
 /* MCUCFG */
 #define CLK_MCU_BUS_SEL			0
-#define CLK_MCU_NR_CLK			1
 
 /* MFGCFG */
 #define CLK_MFG_BG3D			0
 #define CLK_MFG_MBIST_DIAG		1
-#define CLK_MFG_NR_CLK			2
 
 /* MMSYS */
 #define CLK_MM_MM_MDP_RDMA0		0
@@ -331,7 +318,6 @@ 
 #define CLK_MM_MM_DPI0			33
 #define CLK_MM_LVDSTX_PXL		34
 #define CLK_MM_LVDSTX_CTS		35
-#define CLK_MM_NR_CLK			36
 
 /* IMGSYS */
 #define CLK_CAM_LARB2			0
@@ -342,17 +328,14 @@ 
 #define CLK_CAMSV1			5
 #define CLK_CAM_FDVT			6
 #define CLK_CAM_WPE			7
-#define CLK_CAM_NR_CLK			8
 
 /* VDECSYS */
 #define CLK_VDEC_VDEC			0
 #define CLK_VDEC_LARB1			1
-#define CLK_VDEC_NR_CLK			2
 
 /* VENCSYS */
 #define CLK_VENC			0
 #define CLK_VENC_JPGENC			1
-#define CLK_VENC_NR_CLK			2
 
 /* APUSYS */
 #define CLK_APU_IPU_CK			0
@@ -361,6 +344,5 @@ 
 #define CLK_APU_IF_CK			3
 #define CLK_APU_EDMA			4
 #define CLK_APU_AHB			5
-#define CLK_APU_NR_CLK			6
 
 #endif /* _DT_BINDINGS_CLK_MT8365_H */