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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:30 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Subject: [PATCH net-next 15/30] net: dsa: mt7530: set TRGMII RD TAP if trgmii is being used Date: Mon, 22 May 2023 15:15:17 +0300 Message-Id: <20230522121532.86610-16-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230522_051636_593000_5616B270 X-CRM114-Status: GOOD ( 16.33 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mithat.guner@xeront.com, Richard van Schagen , linux-kernel@vger.kernel.org, Richard van Schagen , =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, Bartel Eerdekens , netdev@vger.kernel.org, erkin.bozoglu@xeront.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL This code sets the Read Data (RD) TAP value to 16 for all TRGMII control registers. The for loop iterates over all the TRGMII control registers, and mt7530_rmw() function is used to perform a read-modify-write operation on each register's RD_TAP field to set its value to 16. This operation is used to tune the timing of the read data signal in TRGMII to match the TX signal of the link partner. Run this if trgmii is being used. Since this code doesn't lower the driving, there's no apparent benefit to run this if trgmii is not being used. Add a comment to explain the code. Thanks to 趙皎宏 (Landen Chao) for pointing out what the code does. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 744787e38ecc..f2c1aa9cf7f7 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -404,7 +404,7 @@ static void mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; - u32 ncpo1, ssc_delta, xtal; + u32 ncpo1, ssc_delta, i, xtal; mt7530_clear(priv, MT7530_MHWTRAP, MHWTRAP_P6_DIS); @@ -455,6 +455,11 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) /* Enable the MT7530 TRGMII clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); + + /* Set the Read Data TAP value of the MT7530 TRGMII */ + for (i = 0; i < NUM_TRGMII_CTRL; i++) + mt7530_rmw(priv, MT7530_TRGMII_RD(i), + RD_TAP_MASK, RD_TAP(16)); } } @@ -2209,10 +2214,6 @@ mt7530_setup(struct dsa_switch *ds) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), TD_DM_DRVP(8) | TD_DM_DRVN(8)); - for (i = 0; i < NUM_TRGMII_CTRL; i++) - mt7530_rmw(priv, MT7530_TRGMII_RD(i), - RD_TAP_MASK, RD_TAP(16)); - /* Directly access the PHY registers via C_MDC/C_MDIO. The bit that * enables modifying the hardware trap must be set for this. */