| Message ID | 20230529164605.3552619-4-bero@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add LVTS support for mt8192 | expand |
On 29/05/2023 18:46, Bernhard Rosenkränzer wrote: > From: Balsam CHIHI <bchihi@baylibre.com> > > Add LVTS Driver support for MT8192. > > Co-developed-by : Nícolas F. R. A. Prado <nfraprado@collabora.com> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++ > 1 file changed, 95 insertions(+) > > diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c > index 5ea8a9d569ea6..d5e5214784ece 100644 > --- a/drivers/thermal/mediatek/lvts_thermal.c > +++ b/drivers/thermal/mediatek/lvts_thermal.c > @@ -80,6 +80,7 @@ > #define LVTS_MSR_FILTERED_MODE 1 > > #define LVTS_HW_SHUTDOWN_MT8195 105000 > +#define LVTS_HW_SHUTDOWN_MT8192 105000 > > static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; > static int coeff_b = LVTS_COEFF_B; > @@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { > } > }; > > +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { > + { > + .cal_offset = { 0x04, 0x08 }, > + .lvts_sensor = { > + { .dt_id = MT8192_MCU_BIG_CPU0 }, > + { .dt_id = MT8192_MCU_BIG_CPU1 } > + }, > + .num_lvts_sensor = 2, > + .offset = 0x0, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, > + .mode = LVTS_MSR_FILTERED_MODE, > + }, > + { > + .cal_offset = { 0x0c, 0x10 }, > + .lvts_sensor = { > + { .dt_id = MT8192_MCU_BIG_CPU2 }, > + { .dt_id = MT8192_MCU_BIG_CPU3 } > + }, > + .num_lvts_sensor = 2, > + .offset = 0x100, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, > + .mode = LVTS_MSR_FILTERED_MODE, > + }, > + { > + .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, > + .lvts_sensor = { > + { .dt_id = MT8192_MCU_LITTLE_CPU0 }, > + { .dt_id = MT8192_MCU_LITTLE_CPU1 }, > + { .dt_id = MT8192_MCU_LITTLE_CPU2 }, > + { .dt_id = MT8192_MCU_LITTLE_CPU3 } > + }, > + .num_lvts_sensor = 4, > + .offset = 0x200, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, > + .mode = LVTS_MSR_FILTERED_MODE, > + } > +}; > + > +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { > + { > + .cal_offset = { 0x24, 0x28 }, > + .lvts_sensor = { > + { .dt_id = MT8192_AP_VPU0 }, > + { .dt_id = MT8192_AP_VPU1 } > + }, > + .num_lvts_sensor = 2, > + .offset = 0x0, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, > + }, > + { > + .cal_offset = { 0x2c, 0x30 }, > + .lvts_sensor = { > + { .dt_id = MT8192_AP_GPU0 }, > + { .dt_id = MT8192_AP_GPU1 } > + }, > + .num_lvts_sensor = 2, > + .offset = 0x100, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, > + }, > + { > + .cal_offset = { 0x34, 0x38 }, > + .lvts_sensor = { > + { .dt_id = MT8192_AP_INFRA }, > + { .dt_id = MT8192_AP_CAM }, > + }, > + .num_lvts_sensor = 2, > + .offset = 0x200, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, > + }, > + { > + .cal_offset = { 0x3c, 0x40, 0x44 }, > + .lvts_sensor = { > + { .dt_id = MT8192_AP_MD0 }, > + { .dt_id = MT8192_AP_MD1 }, > + { .dt_id = MT8192_AP_MD2 } > + }, > + .num_lvts_sensor = 3, > + .offset = 0x300, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, > + } > +}; > + > static const struct lvts_data mt8195_lvts_mcu_data = { > .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, > .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), > @@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_data = { > .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), > }; > > +static const struct lvts_data mt8192_lvts_mcu_data = { > + .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, > + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), > +}; > + > +static const struct lvts_data mt8192_lvts_ap_data = { > + .lvts_ctrl = mt8192_lvts_ap_data_ctrl, > + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), > +}; > + > static const struct of_device_id lvts_of_match[] = { > { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, > { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, > + { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, > + { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, > {}, > }; > MODULE_DEVICE_TABLE(of, lvts_of_match);
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 5ea8a9d569ea6..d5e5214784ece 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -80,6 +80,7 @@ #define LVTS_MSR_FILTERED_MODE 1 #define LVTS_HW_SHUTDOWN_MT8195 105000 +#define LVTS_HW_SHUTDOWN_MT8192 105000 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; static int coeff_b = LVTS_COEFF_B; @@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { } }; +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { + { + .cal_offset = { 0x04, 0x08 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_BIG_CPU0 }, + { .dt_id = MT8192_MCU_BIG_CPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset = { 0x0c, 0x10 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_BIG_CPU2 }, + { .dt_id = MT8192_MCU_BIG_CPU3 } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_LITTLE_CPU0 }, + { .dt_id = MT8192_MCU_LITTLE_CPU1 }, + { .dt_id = MT8192_MCU_LITTLE_CPU2 }, + { .dt_id = MT8192_MCU_LITTLE_CPU3 } + }, + .num_lvts_sensor = 4, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + } +}; + +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { + { + .cal_offset = { 0x24, 0x28 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_VPU0 }, + { .dt_id = MT8192_AP_VPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x2c, 0x30 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_GPU0 }, + { .dt_id = MT8192_AP_GPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x34, 0x38 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_INFRA }, + { .dt_id = MT8192_AP_CAM }, + }, + .num_lvts_sensor = 2, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x3c, 0x40, 0x44 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_MD0 }, + { .dt_id = MT8192_AP_MD1 }, + { .dt_id = MT8192_AP_MD2 } + }, + .num_lvts_sensor = 3, + .offset = 0x300, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + } +}; + static const struct lvts_data mt8195_lvts_mcu_data = { .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), @@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_data = { .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), }; +static const struct lvts_data mt8192_lvts_mcu_data = { + .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), +}; + +static const struct lvts_data mt8192_lvts_ap_data = { + .lvts_ctrl = mt8192_lvts_ap_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), +}; + static const struct of_device_id lvts_of_match[] = { { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, + { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, + { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, {}, }; MODULE_DEVICE_TABLE(of, lvts_of_match);