| Message ID | 20230605162030.274395-7-nfraprado@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable decoder for mt8183 | expand |
Il 05/06/23 18:20, Nícolas F. R. A. Prado ha scritto: > From: Yunfei Dong <yunfei.dong@mediatek.com> > > Add node for the hardware decoder present on the MT8183 SoC. > > Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> > Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com> > Signed-off-by: Frederic Chen <frederic.chen@mediatek.com> > Signed-off-by: Alexandre Courbot <acourbot@chromium.org> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 39 ++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 5169779d01df..8bb10ed67e87 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -2019,6 +2019,45 @@ vdecsys: syscon@16000000 { > #clock-cells = <1>; > }; > > + vcodec_dec: video-codec@16020000 { > + compatible = "mediatek,mt8183-vcodec-dec"; > + reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */ > + <0 0x16021000 0 0x800>, /* VDEC_VLD */ > + <0 0x16021800 0 0x800>, /* VDEC_TOP */ > + <0 0x16022000 0 0x1000>, /* VDEC_MC */ > + <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ > + <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ > + <0 0x16025000 0 0x1000>, /* VDEC_PP */ > + <0 0x16026800 0 0x800>, /* VP8_VD */ > + <0 0x16027000 0 0x800>, /* VP6_VD */ > + <0 0x16027800 0 0x800>, /* VP8_VL */ > + <0 0x16028400 0 0x400>; /* VP9_VD */ > + reg-names = "misc", > + "ld", > + "top", > + "cm", > + "ad", > + "av", > + "pp", > + "hwd", > + "hwq", > + "hwb", > + "hwg"; Do we really need one line for each 2/3 characters reg name? :-P Regards, Angelo
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5169779d01df..8bb10ed67e87 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -2019,6 +2019,45 @@ vdecsys: syscon@16000000 { #clock-cells = <1>; }; + vcodec_dec: video-codec@16020000 { + compatible = "mediatek,mt8183-vcodec-dec"; + reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_VLD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_MC */ + <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ + <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VP8_VD */ + <0 0x16027000 0 0x800>, /* VP6_VD */ + <0 0x16027800 0 0x800>, /* VP8_VL */ + <0 0x16028400 0 0x400>; /* VP9_VD */ + reg-names = "misc", + "ld", + "top", + "cm", + "ad", + "av", + "pp", + "hwd", + "hwq", + "hwb", + "hwg"; + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; + mediatek,scp = <&scp>; + power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; + clocks = <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_ACTIVE>; + clock-names = "vdec", "active"; + }; + larb1: larb@16010000 { compatible = "mediatek,mt8183-smi-larb"; reg = <0 0x16010000 0 0x1000>;