From patchwork Fri Sep 1 08:09:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 13372188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06365CA0FF7 for ; Fri, 1 Sep 2023 08:10:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:CC:To:From:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=JinC7Bb2PVa8HrO1FW4navqRVoz1EFqkU53gUdtyeis=; b=bx2CsagIKPPOrQY0ehAATAWLC6 ukvBr4Qkq9UwuvkEmrGKgSuAmxgR/D4gzoZ6m7sZxHpFaT/iGpx+nbIpQ6cLcy3Cm2vOHMwtx0quX jZ031A2xHgdvPPsGW5hzP6sHlED7NNHAXeVjjtfR0BXPglIPJyY7KloR9xIISepfWW+FDXBpd3J1H mHewqVA2PlCGAFx4yQZO1tzMYL0W+MqlsDdC4puomJXj8a4ABaJ+zwhIaukpXPEHRW3iDwcAywoZJ DCWXEqz8OI0p173pr/KEYiU5yfBNnYKdAp2J21ptNeP/jMCEEEVGD5wCfl67v0Bn8qUQ28LMCoOkp urQK92TA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qbzEL-00Geen-1v; Fri, 01 Sep 2023 08:10:13 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qbzEA-00GeVO-0n; Fri, 01 Sep 2023 08:10:04 +0000 X-UUID: f04a39e6489e11ee86758d4a7c00f3a0-20230901 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=JinC7Bb2PVa8HrO1FW4navqRVoz1EFqkU53gUdtyeis=; b=ngCLUNKBUjH2Pi6QFdb/duF/seALtDhkIiCM/545NcsuauDhuf2Lypsg69ACkg51tWq+WkZGmdbpkj4TS6nHNE4p/MekFIYNbJncqJJ7H50g0IeUloxD+c7Uo2giuRzoUSTbvmfH+POtkujy3PDUYjvhLdn8kz54Lj731XZbKFg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:04935352-f6cc-41f1-8df0-eaa287710a76,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:58f90020-33fd-4aaa-bb43-d3fd68d9d5ae,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: f04a39e6489e11ee86758d4a7c00f3a0-20230901 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1407530295; Fri, 01 Sep 2023 01:09:56 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:52 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 09/14] remoteproc: mediatek: Remove dependency of MT8195 SCP L2TCM power control on dual-core SCP Date: Fri, 1 Sep 2023 16:09:30 +0800 Message-ID: <20230901080935.14571-10-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230901_011002_398845_A16FA88D X-CRM114-Status: GOOD ( 18.20 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Previously, SCP core 0 controlled the power of L2TCM and dictated that SCP core 1 could only boot after SCP core 0. To address this constraint, extracted the power control flow of L2TCM and made it shared between both cores, enabling support for arbitrary boot order. The flow for controlling L2TCM power has been incorporated into the mt8195_scp_before_load() and mt8195_scp_stop() APIs, which are respectively invoked during the rproc->ops->start() and rproc->ops->stop() operations. These APIs effectively serve the same purpose as the rproc prepare()/unprepare() APIs." Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 3 ++ drivers/remoteproc/mtk_scp.c | 71 ++++++++++++++++++++++++++------- 2 files changed, 59 insertions(+), 15 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 1438159ae736..fea05bbba9aa 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -106,6 +106,9 @@ struct mtk_scp_of_cluster { size_t l1tcm_size; phys_addr_t l1tcm_phys; struct list_head mtk_scp_list; + /* Prevent concurrent operations of this structure and L2TCM power control. */ + struct mutex cluster_lock; + u32 l2tcm_refcnt; }; struct mtk_scp { diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 685e2c2bb6ee..59d9182a8d1e 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -454,19 +454,37 @@ static int mt8192_scp_before_load(struct mtk_scp *scp) return 0; } -static int mt8195_scp_before_load(struct mtk_scp *scp) +static int mt8195_scp_l2tcm_on(struct mtk_scp *scp) { - /* clear SPM interrupt, SCP2SPM_IPC_CLR */ - writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); + struct mtk_scp_of_cluster *scp_cluster = scp->cluster; + + mutex_lock(&scp_cluster->cluster_lock); + + if (scp_cluster->l2tcm_refcnt == 0) { + /* clear SPM interrupt, SCP2SPM_IPC_CLR */ + writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); + + /* Power on L2TCM */ + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, + MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + } + + scp_cluster->l2tcm_refcnt += 1; + mutex_unlock(&scp_cluster->cluster_lock); + + return 0; +} + +static int mt8195_scp_before_load(struct mtk_scp *scp) +{ writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); - /* enable SRAM clock */ - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, - MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + mt8195_scp_l2tcm_on(scp); + scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); /* enable MPU for all memory regions */ @@ -479,6 +497,8 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp) { scp->data->scp_reset_assert(scp); + mt8195_scp_l2tcm_on(scp); + scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); /* enable MPU for all memory regions */ @@ -645,14 +665,31 @@ static void mt8192_scp_stop(struct mtk_scp *scp) writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG); } +static void mt8195_scp_l2tcm_off(struct mtk_scp *scp) +{ + struct mtk_scp_of_cluster *scp_cluster = scp->cluster; + + mutex_lock(&scp_cluster->cluster_lock); + + if (scp_cluster->l2tcm_refcnt > 0) + scp_cluster->l2tcm_refcnt -= 1; + + if (scp_cluster->l2tcm_refcnt == 0) { + /* Power off L2TCM */ + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, + MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + } + + mutex_unlock(&scp_cluster->cluster_lock); +} + static void mt8195_scp_stop(struct mtk_scp *scp) { - /* Disable SRAM clock */ - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, - MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + mt8195_scp_l2tcm_off(scp); + scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); /* Disable SCP watchdog */ @@ -661,6 +698,8 @@ static void mt8195_scp_stop(struct mtk_scp *scp) static void mt8195_scp_c1_stop(struct mtk_scp *scp) { + mt8195_scp_l2tcm_off(scp); + /* Power off CPU SRAM */ scp_sram_power_off(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); @@ -1108,6 +1147,7 @@ static int scp_probe(struct platform_device *pdev) } INIT_LIST_HEAD(&scp_cluster->mtk_scp_list); + mutex_init(&scp_cluster->cluster_lock); ret = devm_of_platform_populate(dev); if (ret) @@ -1131,6 +1171,7 @@ static void scp_remove(struct platform_device *pdev) rproc_del(scp->rproc); scp_free(scp); } + mutex_destroy(&scp_cluster->cluster_lock); } static const struct mtk_scp_of_data mt8183_of_data = {