| Message ID | 20231023-display-support-v3-12-53388f3ed34b@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add display support for the MT8365-EVK board | expand |
Il 18/04/24 16:17, Alexandre Mergnat ha scritto: > To have a working display through DPI, a workaround has been > implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to > the DPI node. Shortly, that add an extra clock. > > It seems consistent to have the "dpi0_sel" as parent. > Additionnaly, "vpll_dpix" isn't used/managed. > > Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel". > > The new clock tree is: > > clk26m > lvdspll > lvdspll_X (2, 4, 8, 16) > dpi0_sel > mm_dpi0_dpi0 > > Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC") > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> I wonder what CLK_TOP_VPLL_DPIX_EN is for, but since you've ruled it out by removing the dependency, this clock is 100% being disabled because unused and the DPI interface clearly still works. I also wonder if that clock is getting en/disabled by HW control mechanism... ...because that'd make sense, as this is .. well, a DPI clock. That's just out of curiosity though, as I'd really like to understand whenwhatwhy for stuff.... In any case, whether you have an answer or not, this commit is: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cheers!
Quoting Alexandre Mergnat (2024-04-18 07:17:00) > To have a working display through DPI, a workaround has been > implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to > the DPI node. Shortly, that add an extra clock. > > It seems consistent to have the "dpi0_sel" as parent. > Additionnaly, "vpll_dpix" isn't used/managed. > > Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel". > > The new clock tree is: > > clk26m > lvdspll > lvdspll_X (2, 4, 8, 16) > dpi0_sel > mm_dpi0_dpi0 > > Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC") > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> > --- Applied to clk-next
diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/clk-mt8365-mm.c index 01a2ef8f594e..3f62ec750733 100644 --- a/drivers/clk/mediatek/clk-mt8365-mm.c +++ b/drivers/clk/mediatek/clk-mt8365-mm.c @@ -53,7 +53,7 @@ static const struct mtk_gate mm_clks[] = { GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17), GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18), GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19), - GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20), + GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20), GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21), GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22), GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23),
To have a working display through DPI, a workaround has been implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to the DPI node. Shortly, that add an extra clock. It seems consistent to have the "dpi0_sel" as parent. Additionnaly, "vpll_dpix" isn't used/managed. Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel". The new clock tree is: clk26m lvdspll lvdspll_X (2, 4, 8, 16) dpi0_sel mm_dpi0_dpi0 Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC") Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- drivers/clk/mediatek/clk-mt8365-mm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)