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[93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:31 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 12/14] dt-bindings: net: Document Qcom QCA807x PHY package Date: Mon, 20 Nov 2023 14:50:39 +0100 Message-Id: <20231120135041.15259-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231120_055134_444591_A1A34A80 X-CRM114-Status: GOOD ( 16.68 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Document Qcom QCA807x PHY package. Qualcomm QCA807X Ethernet PHY is PHY package of 2 or 5 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. Document the required property to make the PHY package correctly configure and work. Signed-off-by: Christian Marangi --- .../devicetree/bindings/net/qcom,qca807x.yaml | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qcom,qca807x.yaml diff --git a/Documentation/devicetree/bindings/net/qcom,qca807x.yaml b/Documentation/devicetree/bindings/net/qcom,qca807x.yaml new file mode 100644 index 000000000000..c2d59068d015 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,qca807x.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,qca807x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCA807X Ethernet PHY + +maintainers: + - Christian Marangi + - Robert Marko + +description: | + Qualcomm QCA807X Ethernet PHY is PHY package of 2 or 5 + IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and + 1000BASE-T PHY-s. + + They feature 2 SerDes, one for PSGMII or QSGMII connection with + MAC, while second one is SGMII for connection to MAC or fiber. + + Both models have a combo port that supports 1000BASE-X and + 100BASE-FX fiber. + + Each PHY inside of QCA807x series has 4 digitally controlled + output only pins that natively drive LED-s for up to 2 attached + LEDs. Some vendor also use these 4 output for GPIO usage without + attaching LEDs. + + Note that output pins can be set to drive LEDs OR GPIO, mixed + definition are not accepted. + +allOf: + - $ref: ethernet-phy-package.yaml# + +select: + properties: + compatible: + contains: + const: ethernet-phy-package + patternProperties: + ^ethernet-phy(@[a-f0-9]+)?$: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d0b2 + - ethernet-phy-id004d.d0b1 + required: + - compatible + +properties: + global-phys: + maxItems: 2 + + global-phy-names: + items: + - const: combo + - const: pqsgmii + + phy-connection-type: + enum: + - qsgmii + - psgmii + +patternProperties: + ^ethernet-phy(@[a-f0-9]+)?$: + $ref: /schemas/net/ethernet-phy.yaml# + + properties: + gpio-controller: + description: set the output lines as GPIO instead of LEDs + type: boolean + + '#gpio-cells': + description: number of GPIO cells for the PHY + const: 2 + + dependencies: + gpio-controller: ['#gpio-cells'] + + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy-package { + compatible = "ethernet-phy-package"; + #address-cells = <1>; + #size-cells = <0>; + + global-phys = <&qca8075_4>, <&qca8075_psgmii>; + global-phy-names = "combo", "pqsgmii"; + + qca8075_1: ethernet-phy@1 { + compatible = "ethernet-phy-id004d.d0b2"; + reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + qca8075_2: ethernet-phy@2 { + compatible = "ethernet-phy-id004d.d0b2"; + reg = <2>; + + gpio-controller; + #gpio-cells = <2>; + }; + + qca8075_3: ethernet-phy@3 { + compatible = "ethernet-phy-id004d.d0b2"; + reg = <3>; + }; + + qca8075_4: ethernet-phy@4 { + compatible = "ethernet-phy-id004d.d0b2"; + reg = <4>; + }; + + qca8075_pqsgmii: ethernet-phy@5 { + reg = <5>; + }; + }; + };