| Message ID | 20231212121957.19231-8-shawn.sung@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support IGT in display driver | expand |
Hi, Hsiao-chien: On Tue, 2023-12-12 at 20:19 +0800, Hsiao Chien Sung wrote: > Support premultiply and coverage alpha blending in > Mixer. Describe what kind of alpha blending already support for cursor plane. And separate premultiply alpha and coverage alpha to two patches. Regards, CK > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_ethdr.c | 26 +++++++++++++++++++------- > 1 file changed, 19 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c > b/drivers/gpu/drm/mediatek/mtk_ethdr.c > index 73dc4da3ba3b..73c9e3da56a7 100644 > --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c > @@ -5,6 +5,7 @@ > > #include <drm/drm_fourcc.h> > #include <drm/drm_framebuffer.h> > +#include <drm/drm_blend.h> > #include <linux/clk.h> > #include <linux/component.h> > #include <linux/of_device.h> > @@ -35,6 +36,7 @@ > #define MIX_SRC_L0_EN BIT(0) > #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) > #define NON_PREMULTI_SOURCE (2 << 12) > +#define PREMULTI_SOURCE (3 << 12) > #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) > #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) > #define MIX_FUNC_DCM0 0x120 > @@ -153,7 +155,8 @@ void mtk_ethdr_layer_config(struct device *dev, > unsigned int idx, > struct mtk_plane_pending_state *pending = &state->pending; > unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 > | pending->x; > unsigned int align_width = ALIGN_DOWN(pending->width, 2); > - unsigned int alpha_con = 0; > + unsigned int mix_con = NON_PREMULTI_SOURCE; > + bool replace_src_a = false; > > dev_dbg(dev, "%s+ idx:%d", __func__, idx); > > @@ -165,19 +168,28 @@ void mtk_ethdr_layer_config(struct device *dev, > unsigned int idx, > return; > } > > - if (state->base.fb && state->base.fb->format->has_alpha) > - alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA; > + mix_con |= MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA); > > - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? > false : true, > - DEFAULT_9BIT_ALPHA, > + if (state->base.pixel_blend_mode != DRM_MODE_BLEND_COVERAGE) > + mix_con |= PREMULTI_SOURCE; > + > + if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE > || > + (state->base.fb && !state->base.fb->format->has_alpha)) { > + /* > + * Mixer doesn't support CONST_BLD mode, > + * use a trick to make the output equivalent > + */ > + replace_src_a = true; > + } > + > + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, > replace_src_a, MIXER_ALPHA, > pending->x & 1 ? > MIXER_INX_MODE_EVEN_EXTEND : > MIXER_INX_MODE_BYPASS, align_width / > 2 - 1, cmdq_pkt); > > mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, > &mixer->cmdq_base, > mixer->regs, MIX_L_SRC_SIZE(idx)); > mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, > MIX_L_SRC_OFFSET(idx)); > - mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, > mixer->regs, MIX_L_SRC_CON(idx), > - 0x1ff); > + mtk_ddp_write(cmdq_pkt, mix_con, &mixer->cmdq_base, mixer- > >regs, MIX_L_SRC_CON(idx)); > mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, > mixer->regs, MIX_SRC_CON, > BIT(idx)); > }
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index 73dc4da3ba3b..73c9e3da56a7 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -5,6 +5,7 @@ #include <drm/drm_fourcc.h> #include <drm/drm_framebuffer.h> +#include <drm/drm_blend.h> #include <linux/clk.h> #include <linux/component.h> #include <linux/of_device.h> @@ -35,6 +36,7 @@ #define MIX_SRC_L0_EN BIT(0) #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) #define NON_PREMULTI_SOURCE (2 << 12) +#define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) #define MIX_FUNC_DCM0 0x120 @@ -153,7 +155,8 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_pending_state *pending = &state->pending; unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x; unsigned int align_width = ALIGN_DOWN(pending->width, 2); - unsigned int alpha_con = 0; + unsigned int mix_con = NON_PREMULTI_SOURCE; + bool replace_src_a = false; dev_dbg(dev, "%s+ idx:%d", __func__, idx); @@ -165,19 +168,28 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, return; } - if (state->base.fb && state->base.fb->format->has_alpha) - alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA; + mix_con |= MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA); - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true, - DEFAULT_9BIT_ALPHA, + if (state->base.pixel_blend_mode != DRM_MODE_BLEND_COVERAGE) + mix_con |= PREMULTI_SOURCE; + + if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || + (state->base.fb && !state->base.fb->format->has_alpha)) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a = true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); - mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx), - 0x1ff); + mtk_ddp_write(cmdq_pkt, mix_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, BIT(idx)); }
Support premultiply and coverage alpha blending in Mixer. Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-)