[RFC,net-next,7/8] net: dsa: mt7530: correct port capabilities of MT7988

Commit Message

Arınç ÜNAL Jan. 13, 2024, 10:25 a.m. UTC

On the switch on the MT7988 SoC, there are only 4 PHYs. That's port 0 to 3.
Set the internal phy cases to '0 ... 3'.

Signed-off-by: Arınç ÜNAL <[e-mail]>
Acked-by: Daniel Golle <[e-mail]>
---
 drivers/net/dsa/mt7530.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Vladimir Oltean Jan. 15, 2024, 9:42 p.m. UTC | #1

On Sat, Jan 13, 2024 at 01:25:28PM +0300, Arınç ÜNAL wrote:
> On the switch on the MT7988 SoC, there are only 4 PHYs. That's port 0 to 3.
> Set the internal phy cases to '0 ... 3'.
> 
> Signed-off-by: Arınç ÜNAL <[e-mail]>
> Acked-by: Daniel Golle <[e-mail]>
> ---

For this patch to be obviously correct, please make a statement in the
commit message about port 4. It doesn't exist at all?

Daniel Golle Jan. 15, 2024, 10:09 p.m. UTC | #2

On Mon, Jan 15, 2024 at 11:42:38PM +0200, Vladimir Oltean wrote:
> On Sat, Jan 13, 2024 at 01:25:28PM +0300, Arınç ÜNAL wrote:
> > On the switch on the MT7988 SoC, there are only 4 PHYs. That's port 0 to 3.
> > Set the internal phy cases to '0 ... 3'.
> > 
> > Signed-off-by: Arınç ÜNAL <[e-mail]>
> > Acked-by: Daniel Golle <[e-mail]>
> > ---
> 
> For this patch to be obviously correct, please make a statement in the
> commit message about port 4. It doesn't exist at all?

Correct. As shown in Block Diagram 8.1.1.3 on page 125 of
MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
Version: 0.1
Release Date: 2023-10-18
which is available publicly on BananaPi's Wiki[1].

Port 0~3 are TP user ports, Port 6 is internally linked to XGMII of MAC 0.
Port 4 and 5 are not used at all in this design.

[1]: https://wiki.banana-pi.org/Banana_Pi_BPI-R4#Documents

Arınç ÜNAL Jan. 16, 2024, 1:31 p.m. UTC | #3

On 16.01.2024 01:09, Daniel Golle wrote:
> On Mon, Jan 15, 2024 at 11:42:38PM +0200, Vladimir Oltean wrote:
>> On Sat, Jan 13, 2024 at 01:25:28PM +0300, Arınç ÜNAL wrote:
>>> On the switch on the MT7988 SoC, there are only 4 PHYs. That's port 0 to 3.
>>> Set the internal phy cases to '0 ... 3'.
>>>
>>> Signed-off-by: Arınç ÜNAL <[e-mail]>
>>> Acked-by: Daniel Golle <[e-mail]>
>>> ---
>>
>> For this patch to be obviously correct, please make a statement in the
>> commit message about port 4. It doesn't exist at all?
> 
> Correct. As shown in Block Diagram 8.1.1.3 on page 125 of
> MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
> Version: 0.1
> Release Date: 2023-10-18
> which is available publicly on BananaPi's Wiki[1].
> 
> Port 0~3 are TP user ports, Port 6 is internally linked to XGMII of MAC 0.
> Port 4 and 5 are not used at all in this design.
> 
> [1]: https://wiki.banana-pi.org/Banana_Pi_BPI-R4#Documents

Thanks for chiming in Daniel, I will include this on the patch log.

Arınç

Patch

diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 3a02308763ca..e7e7e89d8eca 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -2562,7 +2562,7 @@  static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
 
 	switch (port) {
 	/* Internal PHY */
-	case 0 ... 4:
+	case 0 ... 3:
 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
 			  config->supported_interfaces);
 		break;