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Mon, 25 Mar 2024 20:19:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 25 Mar 2024 20:19:14 +0800 From: yu-chang.lee To: Ulf Hansson , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , , , , Subject: [PATCH 1/2] soc: mediatek: pm-domains: add smi_larb_reset function when power on Date: Mon, 25 Mar 2024 20:19:07 +0800 Message-ID: <20240325121908.3958-2-yu-chang.lee@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240325121908.3958-1-yu-chang.lee@mediatek.com> References: <20240325121908.3958-1-yu-chang.lee@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.880400-8.000000 X-TMASE-MatchedRID: IHaTRTQ81R3SuXLpNqOJSR+WEMjoO9WWTJDl9FKHbrkKogmGusPLb9ro EGQiudNyN/7rnrBxoxyzFPg/Y3uT4hHdGMlurS25JmbrB1j4XwoOPDBPSvoRdDuM/8xRTTt71/H hkIjNCSaZ2BL2I+8mdgpVS+XW10LYBLIUC3yGa8rhuXUWQoMQt30tCKdnhB589yM15V5aWpj6C0 ePs7A07YFInLyeDAoZeviCfOt7+0FMqhlMe0WRKqx4G8Mbv7n+wERbNIEV3QrxkYBDy4DNFQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.880400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 5C20DC049524DA4B3A26E462ADE1E51C709A56F5AAA495AF896EF017A130FFA42000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_053015_659258_C49EDF65 X-CRM114-Status: GOOD ( 17.30 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org This patch avoid mtcmos power glitch from happening by set and clear smi larb reset. Signed-off-by: yu-chang.lee --- drivers/pmdomain/mediatek/mt8188-pm-domains.h | 28 +++++++++ drivers/pmdomain/mediatek/mtk-pm-domains.c | 59 +++++++++++++++++++ drivers/pmdomain/mediatek/mtk-pm-domains.h | 12 ++++ 3 files changed, 99 insertions(+) diff --git a/drivers/pmdomain/mediatek/mt8188-pm-domains.h b/drivers/pmdomain/mediatek/mt8188-pm-domains.h index 06834ab6597c..7bbba4d56a77 100644 --- a/drivers/pmdomain/mediatek/mt8188-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8188-pm-domains.h @@ -573,6 +573,18 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), + .reset_smi = { + SMI_RESET_WR(MT8188_SMI_LARB10_RESET, + MT8188_SMI_LARB10_RESET_ADDR), + SMI_RESET_WR(MT8188_SMI_LARB11A_RESET, + MT8188_SMI_LARB11A_RESET_ADDR), + SMI_RESET_WR(MT8188_SMI_LARB11C_RESET, + MT8188_SMI_LARB11C_RESET_ADDR), + SMI_RESET_WR(MT8188_SMI_LARB11B_RESET, + MT8188_SMI_LARB11B_RESET_ADDR), + SMI_RESET_WR(MT8188_SMI_LARB15_RESET, + MT8188_SMI_LARB15_RESET_ADDR), + }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, [MT8188_POWER_DOMAIN_IPE] = { @@ -583,6 +595,10 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), + .reset_smi = { + SMI_RESET_WR(MT8188_SMI_LARB12_RESET, + MT8188_SMI_LARB12_RESET_ADDR), + }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, [MT8188_POWER_DOMAIN_CAM_VCORE] = { @@ -660,6 +676,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), + .reset_smi = { + SMI_RESET_WR(MT8188_SMI_LARB16A_RESET, + MT8188_SMI_LARB16A_RESET_ADDR), + SMI_RESET_WR(MT8188_SMI_LARB17A_RESET, + MT8188_SMI_LARB17A_RESET_ADDR), + }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, [MT8188_POWER_DOMAIN_CAM_SUBB] = { @@ -670,6 +692,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), + .reset_smi = { + SMI_RESET_WR(MT8188_SMI_LARB16B_RESET, + MT8188_SMI_LARB16B_RESET_ADDR), + SMI_RESET_WR(MT8188_SMI_LARB17B_RESET, + MT8188_SMI_LARB17B_RESET_ADDR), + }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, }; diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index e274e3315fe7..9ab6fa105c8c 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -48,6 +48,8 @@ struct scpsys_domain { struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; + struct regmap **larb; + int num_larb; struct regulator *supply; }; @@ -230,6 +232,39 @@ static int scpsys_regulator_disable(struct regulator *supply) return supply ? regulator_disable(supply) : 0; } +static int _scpsys_smi_larb_reset(const struct smi_reset_data bpd, + struct regmap *regmap) +{ + int ret; + u32 mask = bpd.smi_reset_mask; + + if (!mask) + return 0; + + ret = regmap_set_bits(regmap, bpd.smi_reset_addr, mask); + if (ret) + return ret; + + ret = regmap_clear_bits(regmap, bpd.smi_reset_addr, mask); + if (ret) + return ret; + + return 0; +} + +static int scpsys_smi_larb_reset(struct scpsys_domain *pd) +{ + int ret, i; + + for (i = 0; i < pd->num_larb; i++) { + ret = _scpsys_smi_larb_reset(pd->data->reset_smi[i], pd->larb[i]); + if (ret) + return ret; + } + + return 0; +} + static int scpsys_power_on(struct generic_pm_domain *genpd) { struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd); @@ -279,6 +314,10 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret < 0) goto err_disable_subsys_clks; + ret = scpsys_smi_larb_reset(pd); + if (ret < 0) + goto err_disable_subsys_clks; + ret = scpsys_bus_protect_disable(pd); if (ret < 0) goto err_disable_sram; @@ -355,6 +394,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no struct scpsys_domain *pd; struct device_node *root_node = scpsys->dev->of_node; struct device_node *smi_node; + struct device_node *larb_node; struct property *prop; const char *clk_name; int i, ret, num_clks; @@ -418,6 +458,25 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no return ERR_CAST(pd->smi); } + pd->num_larb = of_count_phandle_with_args(node, "mediatek,larb", NULL); + if (pd->num_larb > 0) { + pd->larb = devm_kcalloc(scpsys->dev, pd->num_larb, sizeof(*pd->larb), GFP_KERNEL); + if (!pd->larb) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < pd->num_larb; i++) { + larb_node = of_parse_phandle(node, "mediatek,larb", i); + if (!larb_node) + return ERR_PTR(-EINVAL); + + pd->larb[i] = device_node_to_regmap(larb_node); + if (IS_ERR(pd->larb[i])) + return ERR_CAST(pd->larb[i]); + } + } else { + pd->num_larb = 0; + } + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) { pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao"); if (IS_ERR(pd->infracfg_nao)) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index aaba5e6b0536..31c2a1bb500f 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -43,6 +43,7 @@ #define PWR_STATUS_USB BIT(25) #define SPM_MAX_BUS_PROT_DATA 6 +#define SPM_MAX_SMI_RESET_DATA 6 enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE = BIT(1), @@ -79,6 +80,16 @@ enum scpsys_bus_prot_flags { INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTSTA1) +#define SMI_RESET_WR(_mask, _addr) { \ + .smi_reset_mask = (_mask), \ + .smi_reset_addr = _addr, \ + } + +struct smi_reset_data { + u32 smi_reset_mask; + u32 smi_reset_addr; +}; + struct scpsys_bus_prot_data { u32 bus_prot_set_clr_mask; u32 bus_prot_set; @@ -110,6 +121,7 @@ struct scpsys_domain_data { u32 ext_buck_iso_mask; u16 caps; const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; + const struct smi_reset_data reset_smi[SPM_MAX_SMI_RESET_DATA]; int pwr_sta_offs; int pwr_sta2nd_offs; };