| Message ID | 20240502103848.5845-12-shawn.sung@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Support IGT in display driver | expand |
Hi, Shawn: On Thu, 2024-05-02 at 18:38 +0800, Shawn Sung wrote: > From: Hsiao Chien Sung <shawn.sung@mediatek.com> > > Support "Pre-multiplied" alpha blending mode on in OVL. > Before this patch, only the "coverage" mode is supported. > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 +++++++++++++++++++++ > ---- > 1 file changed, 35 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index e41fd83e36e79..ad84c2fe57111 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -52,13 +52,16 @@ > #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) > #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) > > +#define OVL_CON_CLRFMT_MAN BIT(23) > #define OVL_CON_BYTE_SWAP BIT(24) > -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) > +#define OVL_CON_RGB_SWAP BIT(25) > #define OVL_CON_CLRFMT_RGB (1 << 12) > #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) > #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) > #define OVL_CON_CLRFMT_UYVY (4 << 12) > #define OVL_CON_CLRFMT_YUYV (5 << 12) > +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) > +#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 | > OVL_CON_CLRFMT_MAN) > #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? > \ > 0 : OVL_CON_CLRFMT_RGB) > #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? > \ > @@ -72,6 +75,8 @@ > #define OVL_CON_VIRT_FLIP BIT(9) > #define OVL_CON_HORZ_FLIP BIT(10) > > +#define OVL_COLOR_ALPHA GENMASK(31, 24) > + > static inline bool is_10bit_rgb(u32 fmt) > { > switch (fmt) { > @@ -296,7 +301,13 @@ void mtk_ovl_config(struct device *dev, unsigned > int w, > if (w != 0 && h != 0) > mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl- > >cmdq_reg, ovl->regs, > DISP_REG_OVL_ROI_SIZE); > - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_ROI_BGCLR); > + > + /* > + * The background color must be opaque black (ARGB), > + * otherwise the alpha blending will have no effect > + */ > + mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl- > >cmdq_reg, > + ovl->regs, DISP_REG_OVL_ROI_BGCLR); > > mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_RST); > mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_RST); > @@ -372,7 +383,8 @@ void mtk_ovl_layer_off(struct device *dev, > unsigned int idx, > DISP_REG_OVL_RDMA_CTRL(idx)); > } > > -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, > unsigned int fmt) > +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, > unsigned int fmt, > + unsigned int blend_mode) > { > /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" > * is defined in mediatek HW data sheet. > @@ -391,21 +403,35 @@ static unsigned int ovl_fmt_convert(struct > mtk_disp_ovl *ovl, unsigned int fmt) > return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; > case DRM_FORMAT_RGBX8888: > case DRM_FORMAT_RGBA8888: > + return blend_mode == DRM_MODE_BLEND_COVERAGE ? > + OVL_CON_CLRFMT_ARGB8888 : > + OVL_CON_CLRFMT_PARGB8888; > case DRM_FORMAT_RGBX1010102: > case DRM_FORMAT_RGBA1010102: > return OVL_CON_CLRFMT_ARGB8888; > case DRM_FORMAT_BGRX8888: > case DRM_FORMAT_BGRA8888: > + return OVL_CON_BYTE_SWAP | > + (blend_mode == DRM_MODE_BLEND_COVERAGE ? > + OVL_CON_CLRFMT_ARGB8888 : > + OVL_CON_CLRFMT_PARGB8888); > case DRM_FORMAT_BGRX1010102: > case DRM_FORMAT_BGRA1010102: > return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; > case DRM_FORMAT_XRGB8888: > case DRM_FORMAT_ARGB8888: > + return blend_mode == DRM_MODE_BLEND_COVERAGE ? > + OVL_CON_CLRFMT_RGBA8888 : > + OVL_CON_CLRFMT_PARGB8888; > case DRM_FORMAT_XRGB2101010: > case DRM_FORMAT_ARGB2101010: > return OVL_CON_CLRFMT_RGBA8888; > case DRM_FORMAT_XBGR8888: > case DRM_FORMAT_ABGR8888: > + return OVL_CON_RGB_SWAP | > + (blend_mode == DRM_MODE_BLEND_COVERAGE ? > + OVL_CON_CLRFMT_RGBA8888 : > + OVL_CON_CLRFMT_PARGB8888); Originally when coverage mode, XBGR8888 and ABGR8888 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP but this patch return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_RGB_SWAP This modification is not related to pre-multiplied blending, so separate to another patch. > case DRM_FORMAT_XBGR2101010: > case DRM_FORMAT_ABGR2101010: > return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; > @@ -429,6 +455,7 @@ void mtk_ovl_layer_config(struct device *dev, > unsigned int idx, > unsigned int fmt = pending->format; > unsigned int offset = (pending->y << 16) | pending->x; > unsigned int src_size = (pending->height << 16) | pending- > >width; > + unsigned int blend_mode = state->base.pixel_blend_mode; > unsigned int ignore_pixel_alpha = 0; > unsigned int con; > bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR; > @@ -447,9 +474,11 @@ void mtk_ovl_layer_config(struct device *dev, > unsigned int idx, > return; > } > > - con = ovl_fmt_convert(ovl, fmt); > - if (state->base.fb && state->base.fb->format->has_alpha) > - con |= OVL_CON_AEN | OVL_CON_ALPHA; > + con = ovl_fmt_convert(ovl, fmt, blend_mode); > + if (state->base.fb) { > + con |= OVL_CON_AEN; > + con |= state->base.alpha & OVL_CON_ALPHA; This looks like plane alpha (The whole video plane use single alpha value), not related to pre-multiplied blending. So separate to another patch. Regards, CK > + } > > if (state->base.fb && !state->base.fb->format->has_alpha) > ignore_pixel_alpha = OVL_CONST_BLEND;
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index e41fd83e36e79..ad84c2fe57111 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -52,13 +52,16 @@ #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) +#define OVL_CON_CLRFMT_MAN BIT(23) #define OVL_CON_BYTE_SWAP BIT(24) -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_RGB_SWAP BIT(25) #define OVL_CON_CLRFMT_RGB (1 << 12) #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_CLRFMT_MAN) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -72,6 +75,8 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) +#define OVL_COLOR_ALPHA GENMASK(31, 24) + static inline bool is_10bit_rgb(u32 fmt) { switch (fmt) { @@ -296,7 +301,13 @@ void mtk_ovl_config(struct device *dev, unsigned int w, if (w != 0 && h != 0) mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_SIZE); - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR); + + /* + * The background color must be opaque black (ARGB), + * otherwise the alpha blending will have no effect + */ + mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_ROI_BGCLR); mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); @@ -372,7 +383,8 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx, DISP_REG_OVL_RDMA_CTRL(idx)); } -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt, + unsigned int blend_mode) { /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" * is defined in mediatek HW data sheet. @@ -391,21 +403,35 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: + return blend_mode == DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_RGBX1010102: case DRM_FORMAT_RGBA1010102: return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + return OVL_CON_BYTE_SWAP | + (blend_mode == DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888); case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + return blend_mode == DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: + return OVL_CON_RGB_SWAP | + (blend_mode == DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PARGB8888); case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; @@ -429,6 +455,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, unsigned int fmt = pending->format; unsigned int offset = (pending->y << 16) | pending->x; unsigned int src_size = (pending->height << 16) | pending->width; + unsigned int blend_mode = state->base.pixel_blend_mode; unsigned int ignore_pixel_alpha = 0; unsigned int con; bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR; @@ -447,9 +474,11 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, return; } - con = ovl_fmt_convert(ovl, fmt); - if (state->base.fb && state->base.fb->format->has_alpha) - con |= OVL_CON_AEN | OVL_CON_ALPHA; + con = ovl_fmt_convert(ovl, fmt, blend_mode); + if (state->base.fb) { + con |= OVL_CON_AEN; + con |= state->base.alpha & OVL_CON_ALPHA; + } if (state->base.fb && !state->base.fb->format->has_alpha) ignore_pixel_alpha = OVL_CONST_BLEND;