From patchwork Fri Jun 14 02:46:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 13697744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CD7FC27C7B for ; Fri, 14 Jun 2024 02:46:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To:From:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VrnEiZMzhbeTqsOlS9Sgz5XKj3UyAknKvFxKQ7N/8V0=; b=TdaXTspFSjsVLVKUq3xUVwoeSB trG9uKoYWhZOcqHAzeWnV5rOa4gdrjIFJBDB6StRFZU9uGfk/jVE8iw4ikYRSnl69VGN9vRh09F4z oCeGtljiNjkUlitOAVApb4m2IKRag69jR1iVJBNallz/u9a1IIYmCK8rRVxtnSnf8QVwhgnK/Wv/B Tnjs2cM2IA+uAojBHxizmQ3vMoP74VYxEACYq6+prFh6epvW1RAC9CKght3y7wvoVUtNa4/DjNMxe B//+0ZAcFp1uob7Qik5hNWdbSIyejxrQLH8UE/xpQVsga+iCP3NiWAYg0ZQ/PXynNcI832ovftJYs OWd0Enng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHwxf-00000001A3i-3KHI; Fri, 14 Jun 2024 02:46:43 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHwxR-000000019sI-14Pp; Fri, 14 Jun 2024 02:46:30 +0000 X-UUID: 4a3ddb6629f811efaf04eb0598667787-20240613 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VrnEiZMzhbeTqsOlS9Sgz5XKj3UyAknKvFxKQ7N/8V0=; b=iJ3hBxiLYXUqC3cZkmzoswl0C9cEurBhmkuQ4/kWLk4TrOPfCj0jEWs473ShFMLmlPcdho9x7GE66F+N92jHsBwVhEKxa3RIRhfloyssbWJJunZBguZvNszvD2vuBXRTP+8q6+jWWWoVPDBPRLpQZ/rfc+fQyjnbl6fnZCOEeG0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:504123ac-8790-44a9-828e-a5c3fb6e59db,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:393d96e,CLOUDID:983d8f44-4544-4d06-b2b2-d7e12813c598,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4a3ddb6629f811efaf04eb0598667787-20240613 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 823599102; Thu, 13 Jun 2024 19:46:24 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:22 +0800 From: Shawn Sung To: Chun-Kuang Hu Subject: [PATCH v9 01/21] soc: mediatek: Disable 9-bit alpha in ETHDR Date: Fri, 14 Jun 2024 10:46:00 +0800 Message-ID: <20240614024620.19011-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240613_194629_339768_A6681D07 X-CRM114-Status: GOOD ( 12.54 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , Sean Paul , Jason Chen , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, CK Hu , "Nancy . Lin" , linux-mediatek@lists.infradead.org, Bibby Hsieh , Matthias Brugger , Philipp Zabel , Hsiao Chien Sung , David Airlie , linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Hsiao Chien Sung When 9-bit alpha is enabled, its value will be converted from 0-255 to 0-256 (255 = not defined). This is designed for special HDR related calculation, which should be disabled by default, otherwise, alpha blending will not work correctly. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 3 +-- drivers/soc/mediatek/mtk-mmsys.c | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index ac4132210585..29673611fa75 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -50,7 +50,6 @@ #define MIXER_INX_MODE_BYPASS 0 #define MIXER_INX_MODE_EVEN_EXTEND 1 -#define DEFAULT_9BIT_ALPHA 0x100 #define MIXER_ALPHA_AEN BIT(8) #define MIXER_ALPHA 0xff #define ETHDR_CLK_NUM 13 @@ -169,7 +168,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA; mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true, - DEFAULT_9BIT_ALPHA, + MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index afb2c40c85c1..00eff18a3bce 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -236,6 +236,7 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, alpha << 16 | alpha, cmdq_pkt); + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), alpha_sel << (19 + idx), cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,