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[1/4] arm64: dts: mediatek: mt7986: fix the switch reset line on BPI-R3

Message ID 20240627075856.2314804-2-leith@bade.nz (mailing list archive)
State New
Headers show
Series fix up pin definitions for BPI-R3 board | expand

Commit Message

Leith Bade June 27, 2024, 7:58 a.m. UTC 
The current GPIO definition for the MT7531 switch reset line incorrectly
specifies a pin GPIO_0 (GPIO5) that is connected to the boot mode
selection DIP switch (SW1).

In the public schematic for the BPI-R3 (titled "BPI-R3-MT7986A",
revision "V1.1", sheet 4), the SPI1_CS (GPIO32) pin of the MT7986 (U1E)
is connected to the GbE_RESET net.

Frank Wunderlich has told me, via the Banana Pi forum, that this GbE_RESET
net connects to the MT7531 reset line in the private part of the shematic
he has a copy of.

Signed-off-by: Leith Bade <leith@bade.nz>
---
 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
index ed79ad1ae871..951612ea1e66 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -206,7 +206,7 @@  switch: switch@31 {
 		interrupt-controller;
 		#interrupt-cells = <1>;
 		interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&pio 32 GPIO_ACTIVE_HIGH>;
 	};
 };